PIC18F26K20-I/ML Microchip Technology, PIC18F26K20-I/ML Datasheet - Page 261

• Manufacturer Part Number: PIC18F26K20-I/ML
• Description: IC PIC MCU FLASH 32KX16 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-I/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3936Byte
• Cpu Speed: 64MHz
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Details

FIGURE 18-12:
TABLE 18-8:
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
Name
CREN bit
SREN bit
bit SREN
RCIF bit
RXREG
RX/DT
Write to
Read
pin
Reserved in 28-pin devices; always maintain these bits clear.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit 0
bit 1
DTRXP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
bit 2
CKTXP
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
bit 3
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
PIC18F2XK20/4XK20
bit 4
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
bit 6
bit 7
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
DS41303G-page 261
Bit 0
on page
Values
Reset
59
62
62
62
61
61
61
61
61
61
‘0’