ATTINY44-15SSZ Atmel, ATTINY44-15SSZ Datasheet - Page 81
![IC MCU AVR 4K FLASH 15MHZ 14SOIC](/photos/7/39/73946/313-14-soic_sml.jpg)
ATTINY44-15SSZ
Manufacturer Part Number
ATTINY44-15SSZ
Description
IC MCU AVR 4K FLASH 15MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY44-15SSZ.pdf
(225 pages)
Specifications of ATTINY44-15SSZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / Rohs Status
Details
Other names
Q3447517
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-15SSZ
Manufacturer:
ATMEL
Quantity:
350
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7701E–AVR–02/11
Figure 13-7. Phase Correct PWM Mode, Timing Diagram
The timer/counter overflow flag (TOV0) is set each time the counter reaches bottom. The inter-
rupt flag can be used to generate an interrupt each time the counter reaches the bottom value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 bits to three. Setting the COM0A0
bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This
option is not available for the OC0B pin (See
will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC0x register at the compare match
between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x
register at compare match between OCR0x and TCNT0 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
The variable N represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to bottom, the
output will be continuously low, and if set equal to max the output will be continuously high for
non-inverted PWM mode. For inverted PWM, the output will have the opposite logic values.
At the very start of period 2 in
even though there is no compare match. The point of this transition is to guarantee symmetry
around bottom. There are two cases that give a transition without a compare match.
TCNTn
OCn
OCn
Period
Atmel ATtiny24/44/84 [Preliminary]
1
Figure 13-7 on page 81
f
OCnxPCPWM
2
Table 13-4 on page
=
-------------------- -
N
f
clk_I/O
510
OCn has a transition from high to low
3
85). The actual OC0x value
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
81
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