ATTINY44-15SSZ Atmel, ATTINY44-15SSZ Datasheet - Page 78
![IC MCU AVR 4K FLASH 15MHZ 14SOIC](/photos/7/39/73946/313-14-soic_sml.jpg)
ATTINY44-15SSZ
Manufacturer Part Number
ATTINY44-15SSZ
Description
IC MCU AVR 4K FLASH 15MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY44-15SSZ.pdf
(225 pages)
Specifications of ATTINY44-15SSZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / Rohs Status
Details
Other names
Q3447517
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-15SSZ
Manufacturer:
ATMEL
Quantity:
350
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- Download datasheet (4Mb)
13.7.3
78
Atmel ATtiny24/44/84 [Preliminary]
Fast PWM Mode
The timing diagram for the CTC mode is shown in
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then
counter (TCNT0) is cleared.
Figure 13-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the top value by using the
OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the top value. However, changing top to a value close to bottom when the counter is running
with no or a low prescaler value must be done with care since the CTC mode does not have
the double buffering feature. If the new value written to OCR0A is lower than the current value
of TCNT0, the counter will miss the compare match. The counter will then have to count to its
maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its log-
ical level on each compare match by setting the compare output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction
for the pin is set to output. The waveform generated will have a maximum frequency of
0
lowing equation:
The variable N represents the prescale factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV0 flag is set on the same timer clock cycle on
which the counter counts from max to 0x00.
The fast pulse width modulation, or fast PWM, mode (WGM02:0 = 3 or 7) provides a high-fre-
quency PWM waveform generation option. The fast PWM mode differs from the other PWM
option by its single-slope operation. The counter counts from bottom to top then restarts from
bottom. Top is defined as 0xFF when WGM2:0 = 3, and as OCR0A when WGM2:0 = 7. In
non-inverting compare output mode, the output compare (OC0x) is cleared on the compare
match between TCNT0 and OCR0x, and set at bottom. In inverting compare output mode, the
output is set on compare match and cleared at bottom. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slope operation.
f
OCnx
= f
clk_I/O
TCNTn
OCn
(Toggle)
Period
=
/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the fol-
------------------------------------------------------ -
2
N
f
clk_I/O
1
+
1
OCRnx
2
3
Figure 13-5 on page
4
78. The counter value
OCnx Interrupt Flag Set
(COMnx1:0 = 1)
7701E–AVR–02/11
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