ATTINY45-15SZ Atmel, ATTINY45-15SZ Datasheet - Page 90

• Manufacturer Part Number: ATTINY45-15SZ
• Description: MCU AVR 4K FLASH 15MHZ 8-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY45-15SZ

• Package / Case: 8-SOIC (3.9mm Width)
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 6
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.11
90
ATtiny25/45/85
Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C -
OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the
PB1(OC1A) and PB3(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB2(OC1B). As
default non-overlapping times for complementary output pairs are zero, but they can be inserted
using a Dead Time Generator (see description on page 100).
Figure 14-4. The PWM Output Pair
When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs
are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the
Timer/Counter1 Control Register A - TCCR1, as shown in
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output
compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set
an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.
Table 14-4.
Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data
value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B
when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM
pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See
example.
COM11
0
0
1
1
PWM1x
PWM1x
Compare Mode Select in PWM Mode
t
non-overlap
COM10
0
1
0
1
=0
Effect on Output Compare Pins
OC1x not connected.
OC1x not connected.
OC1x cleared on compare match. Set whenTCNT1 = $01.
OC1x set on compare match. Cleared when TCNT1 = $00.
OC1x cleared on compare match. Set when TCNT1 = $01.
OC1x not connected.
OC1x Set on compare match. Cleared when TCNT1= $01.
OC1x not connected.
t
non-overlap
=0
x = A or B
Table
14-4.
Figure 14-5
7598H–AVR–07/09
for an