ATTINY45-15SZ Atmel, ATTINY45-15SZ Datasheet - Page 62

• Manufacturer Part Number: ATTINY45-15SZ
• Description: MCU AVR 4K FLASH 15MHZ 8-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY45-15SZ

• Package / Case: 8-SOIC (3.9mm Width)
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 6
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.2
12.2
12.3
62
Timer/Counter Clock Sources
Counter Unit
ATtiny25/45/85
Definitions
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B).
set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare
interrupt request.
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions below are also used extensively throughout the document.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
12-2
Figure 12-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surroundings.
See “Output Compare Unit” on page 63.
“Timer/Counter Prescaler” on page
DATA BUS
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is dependent
on the mode of operation.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TCNTn
direction
count
clear
bottom
Control Logic
78.
for details. The Compare Match event will also
top
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
7598H–AVR–07/09
Tn
Figure