ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 86
![MCU AVR 2K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY24-15MZ
Manufacturer Part Number
ATTINY24-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24-15MZ.pdf
(225 pages)
Specifications of ATTINY24-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
SPI/UART
Total Internal Ram Size
128Byte
# I/os (max)
12
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
20
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.9.2
86
Atmel ATtiny24/44/84 [Preliminary]
TCCR0B – Timer/Counter Control Register B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to logical zero
when TCCR0B is written when operating in PWM mode. When writing a logical one to the
FOC0A bit, an immediate compare match is forced on the waveform generation unit. The
OC0A output is changed according to its COM0A1:0 bit settings. Note that the FOC0A bit is
implemented as a strobe. Therefore, it is the value present in the COM0A1:0 bits that deter-
mines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to logical zero
when TCCR0B is written when operating in PWM mode. When writing a logical one to the
FOC0B bit, an immediate compare match is forced on the waveform generation unit. The
OC0B output is changed according to its COM0B1:0 bit settings. Note that the FOC0B bit is
implemented as a strobe. Therefore, it is the value present in the COM0B1:0 bits that deter-
mines the effect of the forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84, and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Bit
0x33 (0x53)
Read/Write
Initial Value
FOC0A
W
7
0
FOC0B
W
“TCCR0A – Timer/Counter Control Register A” on page
6
0
R
5
–
0
R
4
–
0
WGM02
R/W
3
0
CS02
R/W
2
0
CS01
R/W
1
0
CS00
R/W
0
0
7701D–AVR–09/10
83.
TCCR0B
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