ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 53
![MCU AVR 2K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY24-15MZ
Manufacturer Part Number
ATTINY24-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24-15MZ.pdf
(225 pages)
Specifications of ATTINY24-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
SPI/UART
Total Internal Ram Size
128Byte
# I/os (max)
12
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
20
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.2.3
11.2.4
7701D–AVR–09/10
GIFR – General Interrupt Flag Register
PCMSK1 – Pin Change Mask Register 1
• Bit 4– PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change inter-
rupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The
corresponding interrupt of pin change interrupt request is executed from the PCI0 interrupt
vector. PCINT7..0 pins are enabled individually by the PCMSK0 register.
• Bits 7, 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes
set (logical one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT0 is configured as a level interrupt.
• Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT11..8 pin triggers an interrupt request, PCIF1 becomes set
(logical one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump
to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 4– PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF becomes set
(logical one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump
to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 7, 4– Res: Reserved Bits
These bits are reserved bits in the Atmel
Bit
0x3A (0x5A
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
R
7
–
0
R
7
–
0
INTF0
R
6
–
0
R/W
6
0
Atmel ATtiny24/44/84 [Preliminary]
PCIF1
R
0
5
–
R/W
5
0
®
R
4
–
0
PCIF0
ATtiny24/44/84 and will always read as zero.
R/W
4
0
PCINT11
R/W
3
0
R
3
–
0
PCINT10
R/W
2
0
R
2
–
0
PCINT9
R/W
1
0
R
1
–
0
PCINT8
R/W
0
0
0
–
R
0
PCMSK1
GIFR
53
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