ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 134
![MCU AVR 2K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY24-15MZ
Manufacturer Part Number
ATTINY24-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24-15MZ.pdf
(225 pages)
Specifications of ATTINY24-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
SPI/UART
Total Internal Ram Size
128Byte
# I/os (max)
12
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
20
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.2
17.2.1
17.2.2
134
Register Description
Atmel ATtiny24/44/84 [Preliminary]
ADCSRB – ADC Control and Status Register B
ACSR – Analog Comparator Control and Status Register
Table 17-1.
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logical one and the ADC is switched off (ADEN in ADCSRA is zero),
the ADC multiplexer selects the negative input to the analog comparator. When this bit is writ-
ten logical zero, AIN1 is applied to the negative input of the analog comparator. For a detailed
description of this bit, see
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logical one, the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator. This will reduce power consumption
in active and idle mode. When changing the ACD bit, the analog comparator interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the ana-
log comparator. When this bit is cleared, AIN0 is applied to the positive input of the analog
comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the analog comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of one to two clock cycles.
Bit
0x03 (0x23)
Read/Write
Initial Value
Bit
0x08 (0x28)
Read/Write
Initial Value
ACME
0
1
1
1
1
1
1
1
1
1
Analog Comparator Multiplexed Input
ACD
R/W
R/W
BIN
ADEN
7
0
7
0
x
1
0
0
0
0
0
0
0
0
ACBG
ACME
R/W
R/W
6
0
“Analog Comparator Multiplexed Input” on page
6
0
MUX4..0
00000
00001
00010
00011
00100
00101
00110
00111
xx
xx
ACO
R/W
N/A
5
R
5
–
0
ADLAR
Analog Comparator Negative Input
AIN1
AIN1
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
R/W
ACI
R/w
4
0
4
0
ACIE
R/W
R
3
0
3
–
0
ADTS2
ACIC
R/W
R/W
2
0
2
0
ADTS1
ACIS1
R/W
R/W
1
0
1
0
133.
ADTS0
ACIS0
R/W
R/W
0
0
0
0
7701D–AVR–09/10
ADCSRB
ACSR
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