ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 168
![MCU AVR 2K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY24-15MZ
Manufacturer Part Number
ATTINY24-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24-15MZ.pdf
(225 pages)
Specifications of ATTINY24-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
SPI/UART
Total Internal Ram Size
128Byte
# I/os (max)
12
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
20
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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21.6.2
Table 21-11. Serial Programming Instruction Set
168
Instruction/Operation
Programming Enable
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
Load Instructions
Load Extended Address byte
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
Read Signature Byte
Read Fuse bits
Read Fuse High bits
Read Extended Fuse Bits
Read Calibration Byte
Write Instructions
Write Program Memory Page
Write EEPROM Memory
Write EEPROM Memory Page (page access)
Write Lock bits
Atmel ATtiny24/44/84 [Preliminary]
Serial Programming Instruction set
(6)
(1)
8. Power-off sequence (if needed):
Table 21-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Table 21-11 on page 168
Symbol
t
t
t
t
WD_FLASH
WD_EEPROM
WD_ERASE
WD_FUSE
Set RESET to “1”.
Turn V
CC
power off.
Byte 1
$AC
$AC
$4D
$C1
$4C
$C0
$C2
$AC
$F0
$A0
$48
$40
$28
$20
$58
$30
$50
$58
$50
$38
and
Figure 21-2 on page 169
adr MSB
adr MSB
adr MSB
adr MSB
adr MSB
Byte 2
$53
$80
$00
$00
$00
$00
$00
$00
$00
$08
$08
$00
$00
$00
$E0
Instruction Format
Minimum Wait Delay
describes the Instruction set.
Extended adr
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
Byte 3
4.5ms
4.0ms
4.0ms
4.5ms
$00
$00
$00
$00
$00
$00
$00
$00
$00
high data byte out
low data byte out
high data byte in
low data byte in
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
data byte in
data byte in
7701D–AVR–09/10
Byte4
$00
$00
$00
$00
$00
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