ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 118

• Manufacturer Part Number: ATMEGA8A-MUR
• Description: MCU AVR 8KB FLASH 16MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9
17.9.1
8159D–AVR–02/11
Asynchronous Operation of the Timer/Counter
Asynchronous Operation of Timer/Counter2
Figure 17-11
Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-
When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2, and TCCR2.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.
5. Clear the Timer/Counter2 Interrupt Flags.
6. Enable interrupts, if needed.
• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external
• When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a
• When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user
Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe
procedure for switching clock source is:
clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main
clock frequency must be more than four times the Oscillator frequency.
temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the temporary register have been transferred to its
destination. Each of the three mentioned registers have their individual temporary register,
which means that e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To
detect that a transfer to the destination register has taken place, the Asynchronous Status
Register – ASSR has been implemented.
must wait until the written register has been updated if Timer/Counter2 is used to wake up the
device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is
particularly important if the Output Compare2 interrupt is used to wake up the device, since
TCNTn
(clk
(CTC)
OCRn
OCFn
clk
clk
I/O
I/O
Tn
/8)
shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
caler (f
clk_I/O
TOP - 1
/8)
TOP
TOP
BOTTOM
ATmega8A
BOTTOM + 1
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