ATMEGA8A-AUR Atmel, ATMEGA8A-AUR Datasheet - Page 240

• Manufacturer Part Number: ATMEGA8A-AUR
• Description: MCU AVR 8KB FLASH 16MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.9.1
8159D–AVR–02/11
Serial Programming Algorithm
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the Serial Clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega8A, data is clocked on the rising edge of SCK.
When reading data from the ATmega8A, data is clocked on the falling edge of SCK. See
24-8
To program and verify the ATmega8A in the Serial Programming mode, the following sequence
is recommended (See four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable Serial Programming by sending the Programming
3. The Serial Programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The page size is found in
5. Note: If other commands than polling (read) are applied before any write operation
6. The EEPROM array is programmed one byte at a time by supplying the address and
7. Any memory location can be verified by using the Read instruction which returns the
8. At the end of the programming session, RESET can be set high to commence normal
9. Power-off sequence (if needed):
for timing details.
Apply power between V
tems, the programmer can not guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
page
address and data together with the Load Program memory Page instruction. To ensure
correct loading of the page, the data Low byte must be loaded before data High byte is
applied for a given address. The Program memory Page is stored by loading the Write
Program memory Page instruction with the 7 MSB of the address. If polling is not used,
the user must wait at least t
(FLASH, EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect
programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user must
wait at least t
a chip erased device, no 0xFFs in the data file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
229. The memory page is loaded one byte at a time by supplying the 5LSB of the
CC
power off
WD_EEPROM
CC
before issuing the next byte. (See
ck
ck
and GND while RESET and SCK are set to “0”. In some sys-
WD_FLASH
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
before issuing the next page. (See
Table
24-16):
Table 24-15 on page
ck
ck
≥ 12MHz
≥ 12MHz
ATmega8A
Table
Table 24-5 on
24-15).
241). In
Figure
240