ATTINY48-MUR Atmel, ATTINY48-MUR Datasheet - Page 110
ATTINY48-MUR
Manufacturer Part Number
ATTINY48-MUR
Description
MCU AVR 4KB FLASH 12MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY48-MU.pdf
(302 pages)
Specifications of ATTINY48-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY48-MUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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12.11 Register Description
12.11.1
110
ATtiny48/88
TCCR1A – Timer/Counter1 Control Register A
• Bits 7:6 – COM1A[1:0]: Compare Output Mode for Channel A
• Bits 5:4 – COM1B[1:0]: Compare Output Mode for Channel B
The COM1A[1:0] and COM1B[1:0] control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A[1:0] bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B[1:0] bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x[1:0] bits is depen-
dent of the WGM1[3:0] bits setting.
WGM1[3:0] bits are set to a Normal or a CTC mode (non-PWM).
Table 12-2.
Table 12-3
PWM mode.
Table 12-3.
Note:
Bit
(0x80)
Read/Write
Initial Value
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at TOP.
Mode” on page 101.
shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the fast
COM1A1
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
COM1A0/COM1B0
R/W
6
0
for more details.
0
1
0
1
0
1
0
1
COM1B1
R/W
Table 12-2
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
Description
Normal port operation, OC1A/OC1B disconnected.
WGM1[3:0] = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at TOP
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at TOP
shows the COM1x[1:0] bit functionality when the
(1)
R
3
–
0
R
2
–
0
WGM11
R/W
1
0
WGM10
See “Fast PWM
R/W
0
0
8008G–AVR–04/11
TCCR1A
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