ATTINY44-20MUR Atmel, ATTINY44-20MUR Datasheet - Page 56
ATTINY44-20MUR
Manufacturer Part Number
ATTINY44-20MUR
Description
MCU AVR 4KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24-20MU.pdf
(238 pages)
Specifications of ATTINY44-20MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-20MUR
Manufacturer:
ATMEL
Quantity:
2 100
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10.1.2
10.1.3
10.1.4
56
ATtiny24/44/84
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b10) as an intermediate step.
Table 10-1
Table 10-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
DDxn
0
0
0
1
1
PORTxn
summarizes the control signals for the pin value.
INSTRUCTIONS
0
1
1
0
1
Port Pin Configurations
SYSTEM CLK
SYNC LATCH
PINxn
(in MCUCR)
r17
PUD
X
X
X
0
1
Figure 10-2 on page
XXX
Output
Output
Input
Input
Input
I/O
t
pd, max
Pull-up
0x00
Yes
No
No
No
No
XXX
55, the PINxn Register bit and the preced-
t
pd, min
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
pd,max
in r17, PINx
and t
pd,min
0xFF
respectively.
8006K–AVR–10/10
Figure 10-3
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