ATTINY44-20MUR Atmel, ATTINY44-20MUR Datasheet - Page 102
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ATTINY44-20MUR
Manufacturer Part Number
ATTINY44-20MUR
Description
MCU AVR 4KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24-20MU.pdf
(238 pages)
Specifications of ATTINY44-20MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-20MUR
Manufacturer:
ATMEL
Quantity:
2 100
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102
ATtiny24/44/84
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on
quency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in
the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be
set when a compare match occurs.
Figure 12-9. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x
Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1
is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP.
The interrupt flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
As
mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the
length of the rising and the falling slopes will always be equal. This gives symmetrical output
pulses and is therefore frequency correct.
TCNTn
OCnx
OCnx
Period
Figure 12-9 on page 102
1
shows the output generated is, in contrast to the phase correct
Figure 12-9 on page
R
PFCPWM
2
=
3
log
---------------------------------- -
(
log
TOP
2 ( )
102. The figure shows phase and fre-
+
1
)
4
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
8006K–AVR–10/10
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