PIC16F684T-E/ST Microchip Technology, PIC16F684T-E/ST Datasheet
PIC16F684T-E/ST
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PIC16F684T-E/ST Summary of contents
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... Microchip Technology Inc. PIC16F684 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41202F ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash/Data EEPROM retention: > 40 years Program Memory Device Flash (words) PIC16F684 2048 © 2007 Microchip Technology Inc. PIC16F684 Low-Power Features: • Standby Current 2.0V, typical • Operating Current μ kHz, 2.0V, typical - 220 μ MHz, 2.0V, typical • Watchdog Timer Current μ ...
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... P1B — — CCP1/P1A — — — — — — — /ICSPCLK REF Basic Y ICSPDAT/ULPWU Y ICSPCLK Y — (2) Y MCLR OSC2/CLKOUT Y OSC1/CLKIN — — — — — — — — — — — — — — © 2007 Microchip Technology Inc. ...
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... C2OUT RC5 4 — — — 16 — — — 13 — — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. RA0/AN0/C1IN+/ICSPDAT/ULPWU 12 1 RA1/AN1/C1IN-/ PIC16F684 RA2/AN2/T0CKI/INT/C1OUT 10 3 RC0/AN4/C2IN Timers CCP Interrupts Pull-ups — — IOC — ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41202F-page 4 © 2007 Microchip Technology Inc. ...
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... Internal Oscillator Block T1G T1CKI Timer0 Timer1 T0CKI Analog-To-Digital Converter V REF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 © 2007 Microchip Technology Inc. INT 13 Data Bus Program Counter RAM 8-Level Stack 128 Bytes (13-Bit) File Registers RAM Addr 9 Addr MUX ...
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... TTL CMOS PORTC I/O CCP1 ST CMOS Capture input/Compare output P1A — CMOS PWM output V Power — Positive supply DD V Power — Ground reference SS CMOS= CMOS compatible input or output = TTL compatible input Description HV = High Voltage XTAL = Crystal © 2007 Microchip Technology Inc. ...
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... Reset Vector Interrupt Vector On-chip Program Memory Wraps to 0000h-07FFh © 2007 Microchip Technology Inc. 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank ...
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... Registers 32 Bytes General Purpose Registers 96 Bytes 6Fh 70 Accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. File Address (1) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah ...
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... IRP and RP1 bits are reserved, always maintain these bits clear. 2: Port pins with analog functions controlled by the ANSEL register will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). © 2007 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
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... IOCA1 IOCA0 --00 0000 33, 105 — — — — VR1 VR0 0-0- 0000 63, 105 EEDAT1 EEDAT0 0000 0000 75, 105 EEADR1 EEADR0 0000 0000 75, 105 WR RD ---- x000 76, 105 ---- ---- 76, 105 xxxx xxxx 71, 105 — — -000 ---- 70, 105 © 2007 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec- ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2007 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits ...
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... PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) OSC 128 256 1 : 128 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IOCA register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. © 2007 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...
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... Disables the Timer1 overflow interrupt DS41202F-page 14 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 C2IE C1IE OSFIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed © 2007 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...
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... Note 1: BOREN<1:0> the Configuration Word register for this bit to control the BOR. DS41202F-page 16 R/W-1 U-0 U-0 SBOREN — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-x POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556). © 2007 Microchip Technology Inc. 2.3.2 STACK The PIC16F684 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1) ...
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... For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. DS41202F-page 18 0 IRP Bank Select 180h NOT USED Bank 1 Bank 2 Bank 3 Indirect Addressing ( File Select Register Location Select 1FFh © 2007 Microchip Technology Inc. ...
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... External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2007 Microchip Technology Inc. The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
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... Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled. DS41202F-page 20 R/W-0 R-1 R-0 (1) IRCF0 OSTS HTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R/W-0 LTS SCS bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Upon restarting the external clock, the device will resume operation time had elapsed. © 2007 Microchip Technology Inc. 3.4 External Clock Modes 3.4.1 OSCILLATOR START-UP TIMER (OST) ...
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... DD ® ® and PIC ® Oscillator Design” ® Oscillator CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic P (3) R (2) R Sleep F OSC2/CLKOUT ( may be required for S varies with the Oscillator mode © 2007 Microchip Technology Inc. ...
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... The user also needs to take into account variation due to tolerance of external RC components used. © 2007 Microchip Technology Inc. 3.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...
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... Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. PIC16F684 3.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING ...
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... IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC IRCF <2:0> System Clock DS41202F-page 26 Start-up Time 2-cycle Sync = 0 2-cycle Sync = 0 0 LFINTOSC turns off unless WDT or FSCM is enabled ¼ 0 Running Running Running © 2007 Microchip Technology Inc. ...
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... Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. PIC16F684 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)” ...
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... FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC T T OST OSC1 0 1 1022 1023 OSC2 Program Counter System Clock DS41202F-page © 2007 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...
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... C2IF C1IF OSFIF TMR2IF Failure Detected Test Value on Value on: Bit 0 all other POR, BOR (1) Resets FOSC0 — — SCS -110 x000 -110 x000 TUN0 ---0 0000 ---u uuuu TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...
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... Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. © 2007 Microchip Technology Inc. port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs ...
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... PORTA operation is being executed, then the RAIF interrupt flag may not get set. R/W-1 R/W-1 R/W-1 ANS4 ANS3 ANS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) . R/W-1 R/W-1 ANS1 ANS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IOCA<5:0>: Interrupt-on-change PORTA Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. © 2007 Microchip Technology Inc. R/W-1 U-0 R/W-1 WPUA4 — WPUA2 U = Unimplemented bit, read as ‘ ...
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... CapDelay and BANKSEL PCON BSF PCON,ULPWUE ;Enable ULP Wake-up BSF IOCA,0 BSF TRISA,0 MOVLW B’10001000’ ;Enable interrupt MOVWF INTCON SLEEP © 2007 Microchip Technology Inc. Application Note ; ;Turn off ;comparators ; ;RA0 to digital I/O ;Output high to ; ;charge capacitor ; ; ;Select RA0 IOC ...
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... RD IOCA Interrupt-on- Change Note 1: Comparator mode and ANSEL determines Analog Input mode. © 2007 Microchip Technology Inc. 4.2.5.2 RA1/AN1/C1IN-/V Figure 4-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • ...
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... WR CK TRISA RD TRISA RD PORTA IOCA RD IOCA Interrupt-on- Change To Timer0 To INT To A/D Converter Note 1: Analog Input mode is generated by ANSEL. BLOCK DIAGRAM OF RA2 (1) Analog Input Mode Weak RAPU C1OUT Enable C1OUT 1 0 I/O Pin (1) Analog Input Mode PORTA © 2007 Microchip Technology Inc. ...
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... IOCA Interrupt-on- Change RD PORTA © 2007 Microchip Technology Inc. 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a Timer1 gate (count enable) • ...
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... BLOCK DIAGRAM OF RA5 INTOSC Mode TMR1LPEN Data Bus WPUA RAPU RD WPUA Oscillator Circuit OSC2 PORTA TRISA INTOSC RD Mode TRISA RD PORTA IOCA EN RD IOCA Interrupt-on- Change RD PORTA To Timer1 Note 1: Timer1 LP Oscillator enabled. DS41202F-page 38 ( Weak V DD I/O Pin © 2007 Microchip Technology Inc. ...
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... RA5 TRISA — — TRISA5 WPUA — — WPUA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2007 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 ANS4 ANS3 ANS2 ANS1 C1INV CIS CM2 ...
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... INITIALIZING PORTC ; ;Init PORTC ;Set RC<4,1:0> to ;digital I/O ; ;digital I/O ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs ;Bank 0 R/W-0 R/W-0 R/W-0 RC2 RC1 RC0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISC2 TRISC1 TRISC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... RD PORTC To Comparators To A/D Converter Note 1: Analog Input mode comes from ANSEL or Comparator mode. © 2007 Microchip Technology Inc. 4.3.3 RC2/AN6/P1D The RC2 is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a digital output from the Enhanced CCP 4 ...
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... TRISC1 BLOCK DIAGRAM OF RC5 PIN V CCP1OUT DD Enable CCP1OUT 1 0 I/O Pin V SS Value on Value on: Bit 0 all other POR, BOR Resets ANS0 1111 1111 1111 1111 CM0 0000 0000 0000 0000 RC0 --xx 0000 --uu uu00 TRISC0 --11 1111 --11 1111 © 2007 Microchip Technology Inc. ...
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... Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter ...
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... T0CKI input and the Timer0 register is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements Section 15.0 “Electrical Specifications”. © 2007 Microchip Technology Inc. as shown in ...
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... TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
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... PIC16F684 NOTES: DS41202F-page 46 © 2007 Microchip Technology Inc. ...
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... ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. Note 1: Timer1 register increments on rising edge. 2: Synchronize does not operate while in Sleep. © 2007 Microchip Technology Inc. 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair ...
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... For writes recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. © 2007 Microchip Technology Inc. ...
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... The device will wake- overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). © 2007 Microchip Technology Inc. PIC16F684 6.9 ECCP Capture/Compare Time Base The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
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... If INTOSC without CLKOUT oscillator is active oscillator is enabled for Timer1 clock oscillator is off Else: This bit is ignored DS41202F-page 50 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. /4) Bit 4 Bit 3 Bit 2 Bit 1 — ...
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... PIC16F684 NOTES: DS41202F-page 52 © 2007 Microchip Technology Inc. ...
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... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> © 2007 Microchip Technology Inc. The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
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... Value on Value on: Bit 0 all other POR, BOR Resets RAIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 © 2007 Microchip Technology Inc. ...
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... Timer1 gate (count enable) • Output synchronization to Timer1 clock input • Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2007 Microchip Technology Inc. PIC16F684 8.1 Comparator Overview A comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output ...
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... D Q Q3*RD CMCON0 EN CL Reset OSC C2SYNC D Q Timer1 (1) clock source CMCON0 D Q Q3*RD CMCON0 EN CL Reset OSC To C1OUT pin To Data Bus Set C1IF bit ). To Timer1 Gate 0 To C2OUT pin 1 To Data Bus Set C2IF bit ). © 2007 Microchip Technology Inc. ...
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... Source Impedance Analog Voltage Threshold Voltage T © 2007 Microchip Technology Inc. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. . The analog SS and V ...
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... REF Comparators Off (Lowest Power) CM<2:0> = 111 C1IN- C1OUT C1IN+ C2IN- C2OUT C2IN+ CIS = Comparator Input Switch (CMCON0<3> Comparator Digital Output C1OUT C2OUT I/O IN (1) Off I C2OUT C1OUT C2OUT I/O IN (1) Off I I/O IN (1) Off I/O © 2007 Microchip Technology Inc. ...
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... In the above modes, both pins remain in Analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch. © 2007 Microchip Technology Inc. 8.4 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage ...
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... A device Reset forces the CMCON0 and CMCON1 registers to their Reset states. This forces the Compar- ator module the Comparator Reset mode (CM<2:0> = 000). Thus, all comparator inputs are analog inputs with the comparator disabled to consume the smallest current possible. © 2007 Microchip Technology Inc. ...
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... Four inputs multiplexed to two comparators 011 = Two common reference comparators 100 = Two independent comparators 101 = One independent comparator 110 = Two common reference comparators with outputs 111 = Comparators off. CxIN pins are configured as digital I/O © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 C1INV CIS CM2 U = Unimplemented bit, read as ‘ ...
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... Figure 8-3) and the Timer1 Block Diagram (Figure 6-1) for more information. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) © 2007 Microchip Technology Inc. R/W-1 R/W-0 T1GSS C2SYNC bit Bit is unknown ...
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... Range Selection bit REF 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ Value Selection bits (0 ≤ VR<3:0> ≤ 15) bit 3-0 VR<3:0>: CV REF When VRR = 1: CV REF When VRR = 0: CV REF © 2007 Microchip Technology Inc. EQUATION 8- (low range REF (high range REF The full range of V the construction of the module ...
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... CM0 0000 0000 0000 0000 ---- --10 ---- --10 RAIF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RA0 --x0 x000 --uu uu00 RC0 --xx 0000 --uu uu00 TRISA0 --11 1111 --11 1111 --11 1111 --11 1111 VR0 0-0- 0000 0-0- 0000 © 2007 Microchip Technology Inc. ...
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... Sleep. Figure 9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM RA0/AN0 RA1/AN1/V REF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 CHS <3:0> © 2007 Microchip Technology Inc. (ADC) allows V DD VCFG = 0 V REF VCFG = 1 A/D GO/DONE ADFM ADON V ...
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... DD ) OSC 4 MHz 1 MHz (2) 2.0 μs 500 ns (2) 1.0 μs 4.0 μs (3) 2.0 μs 8.0 μs (3) 4.0 μs 16.0 μs 8.0 μs (3) 32.0 μs (3) 16.0 μs (3) 64.0 μs (3) 2-6 μs (1,4) 2-6 μs (1,4) © 2007 Microchip Technology Inc. ...
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... Please see Section 9.1.5 “Interrupts” for more information. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. CYCLES ...
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... Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 9.3 Requirements”. © 2007 Microchip Technology Inc. Capture/Com- (1) (2) . “A/D Acquisition ...
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... BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2007 Microchip Technology Inc. PIC16F684 DS41202F-page 69 ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2007 Microchip Technology Inc. R/W-x R/W-x R/W-x ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... S ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD Ω 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED © 2007 Microchip Technology Inc. ...
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... R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h 003h 002h 001h 000h REF © 2007 Microchip Technology Inc Sampling Switch V = 0.6V T ≤ Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range ...
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... RAIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 RA0 --x0 x000 --uu uuuu RC0 --xx 0000 --uu uuuu TRISA0 --11 1111 --11 1111 TRISC0 --11 1111 --11 1111 © 2007 Microchip Technology Inc. ...
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... Bit is set bit 7-0 EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits © 2007 Microchip Technology Inc. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...
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... EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = 1). U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
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... WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. © 2007 Microchip Technology Inc. PIC16F684 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...
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... Value on Value on: Bit 0 all other POR, BOR Resets RAIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 EEDAT0 0000 0000 0000 0000 0000 0000 0000 0000 RD ---- x000 ---- q000 ---- ---- ---- ---- © 2007 Microchip Technology Inc. ...
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... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2007 Microchip Technology Inc. Table 11-1 shows the timer resources required by the ECCP module. ...
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... NEW_CAPT_PS ;Load the W reg with CCPR1L MOVWF CCP1CON TMR1L of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value © 2007 Microchip Technology Inc. ...
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... Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the port I/O data latch. © 2007 Microchip Technology Inc. 11.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...
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... In PWM mode, CCPR1H is a read-only register. DS41202F-page 82 The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 11-4: Period Pulse Width TMR2 = 0 CCP1 TRIS ), or OSC CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4> © 2007 Microchip Technology Inc. ...
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... PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2007 Microchip Technology Inc. EQUATION 11-2: Pulse Width EQUATION 11-3: • OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation ...
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... Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output driver by clearing the associated TRIS bit. © 2007 Microchip Technology Inc. ...
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... Full-Bridge, Forward 01 Full-Bridge, Reverse 11 © 2007 Microchip Technology Inc. The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. ...
Page 88
... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay mode”). DS41202F-page 86 Pulse 0 Width Period (1) (1) Delay Delay © 2007 Microchip Technology Inc. PR2+1 ...
Page 89
... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay mode”). © 2007 Microchip Technology Inc. PIC16F684 Pulse 0 Width Period (1) (1) Delay Delay ...
Page 90
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2007 Microchip Technology Inc. ...
Page 91
... P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 11-10: EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2007 Microchip Technology Inc FET Driver Load FET Driver QB V- ...
Page 92
... EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41202F-page 90 Period (1) Period (1) © 2007 Microchip Technology Inc. ...
Page 93
... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts. © 2007 Microchip Technology Inc. The Full-Bridge mode does not provide dead-band delay ...
Page 94
... PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41202F-page 92 Forward Period Reverse Period OFF – T OFF ON © 2007 Microchip Technology Inc. ...
Page 95
... Drive pins P1B and P1D to ‘0’ Drive pins P1B and P1D to ‘1’ Pins P1B and P1D tri-state © 2007 Microchip Technology Inc. A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘ ...
Page 96
... ECCPASE bit PWM Activity Start of PWM Period DS41202F-page condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears ECCPASE Cleared by Firmware PWM Resumes PWM Resumes © 2007 Microchip Technology Inc. ...
Page 97
... The lower seven bits of the associated PWM1CON register (Register 11-3) sets the delay period in terms of microcontroller instruction cycles ( OSC FIGURE 11-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) © 2007 Microchip Technology Inc. FIGURE 11-16: Period Pulse Width (2) P1A td (2) P1B destructive (1) ...
Page 98
... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 1111 1111 1111 1111 PDC0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 TRISA0 --11 1111 --11 1111 TRISC0 --11 1111 --11 1111 © 2007 Microchip Technology Inc. ...
Page 99
... The INTOSC option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 12-1). © 2007 Microchip Technology Inc. 12.1 Configuration Bits The Configuration bits can be programmed (read as ‘ ...
Page 100
... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41202F-page 98 — FCMEN IESO PWRTE WDTE FOSC2 P = Programmable’ ‘0’ = Bit is cleared (1) (2) (4) DD BOREN1 BOREN0 bit 8 FOSC1 FOSC0 bit Unimplemented bit, read as ‘0’ Bit is unknown © 2007 Microchip Technology Inc. ...
Page 101
... Ripple Counter LFINTOSC Note 1: Refer to the Configuration Word register (Register 12-1). © 2007 Microchip Technology Inc. PIC16F684 Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” ...
Page 102
... V RECOMMENDED MCLR CIRCUIT DD ® PIC R1 MCU 1 kΩ (or greater) R2 MCLR 100 Ω (needed with capacitor) C1 0.1 μF (optional, not critical) to rise to an acceptable level for details (Section 15.0 at the MCLR SS Ω should be used when SS © 2007 Microchip Technology Inc. . ...
Page 103
... DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2007 Microchip Technology Inc drops below V DD running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once V rises above V BOR 64 ms Reset. ...
Page 104
... Configuration Word may have DD Wake-up” and Section 12.3.4 Wake-up from Sleep PWRTE = 1 1024 • T 1024 • T OSC OSC — — Value on Value on: Bit 0 all other POR, BOR (1) Resets BOR --01 --qq --0u --uu C 0001 1xxx 000q quuu © 2007 Microchip Technology Inc. ...
Page 105
... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2007 Microchip Technology Inc. PIC16F684 T PWRT T OST T PWRT T OST ) DD T PWRT T OST DS41202F-page 103 ...
Page 106
... Microchip Technology Inc. Interrupt uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu --uu uuuu ---u uuuu (2) uuuu uuuu ...
Page 107
... Legend unchanged unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution © 2007 Microchip Technology Inc. PIC16F684 Wake-up from Sleep through MCLR Reset ...
Page 108
... Figure 12-10 for timing of wake-up from Sleep through RA2/INT interrupt. Note: The ANSEL and CMCON0 registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. © 2007 Microchip Technology Inc. of their Timer2, ...
Page 109
... ADIF ADIE EEIF EEIE OSFIF OSFIE CCP1IF CCP1IE © 2007 Microchip Technology Inc. 12.4.3 PORTA INTERRUPT-ON-CHANGE An input change on PORTA sets the RAIF bit of the INTCON register. enabled/disabled by setting/clearing the RAIE bit of the INTCON register. Plus, individual pins can be configured through the IOCA register. ...
Page 110
... Inst (0004h) Inst (0005h) Inst (0004h) = instruction cycle time. Latency CY Value on Value on: Bit 0 all other POR, BOR Resets RAIF 0000 0000 0000 0000 IOCA0 --00 0000 --00 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...
Page 111
... STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W © 2007 Microchip Technology Inc. and PIC16F684 DS41202F-page 109 ...
Page 112
... PIC16F684 Section 5.0 “Timer0 Module” for more information. 0 From Timer0 Clock Source 1 PSA WDTPS<3:0> Family of microcontrollers. See (1) Prescaler 8 PS<2:0> To Timer0 1 0 PSA WDT Time-out WDT Cleared Cleared until the end of OST © 2007 Microchip Technology Inc. ...
Page 113
... CONFIG CPD CP MCLRE Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits. © 2007 Microchip Technology Inc. R/W-0 R/W-1 R/W-0 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 114
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 12-10 for more details. © 2007 Microchip Technology Inc. ...
Page 115
... ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2007 Microchip Technology Inc OST (2) T (3) Interrupt Latency ...
Page 116
... ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh ® ICD 2 In-Circuit 20-PIN ICD PINOUT In-Circuit Debug Device ICDCLK ICDDATA Vss 18 RA5 RA0 4 17 RA1 RA4 5 16 RA2 6 RA3 15 RC5 RC0 7 14 RC4 8 RC1 13 RC2 RC3 ICD 10 11 © 2007 Microchip Technology Inc. ...
Page 117
... PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. © 2007 Microchip Technology Inc. PIC16F684 TABLE 13-1: OPCODE FIELD DESCRIPTIONS ...
Page 118
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2007 Microchip Technology Inc. ...
Page 119
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. BCF Syntax: k Operands: Operation: Status Affected: ...
Page 120
... Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. ...
Page 121
... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2007 Microchip Technology Inc. PIC16F684 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 ≤ ...
Page 122
... Move label ] MOVWF f 0 ≤ f ≤ 127 (W) → (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP © 2007 Microchip Technology Inc. ...
Page 123
... Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2007 Microchip Technology Inc. PIC16F684 RETLW Return with literal in W Syntax: [ label ] RETLW k 0 ≤ k ≤ 255 Operands: k → (W); Operation: TOS → PC Status Affected: None ...
Page 124
... Subtract W from literal [ label ] SUBLW k 0 ≤ k ≤ 255 k - (W) → (W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. W > ≤ W<3:0> > k<3:0> W<3:0> ≤ k<3:0> © 2007 Microchip Technology Inc. ...
Page 125
... The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. © 2007 Microchip Technology Inc. PIC16F684 XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k 0 ≤ ...
Page 126
... PIC16F684 NOTES: DS41202F-page 124 © 2007 Microchip Technology Inc. ...
Page 127
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC16F684 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 128
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 129
... Microchip Technology Inc. PIC16F684 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 130
... SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. © 2007 Microchip Technology Inc. ® ...
Page 131
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. ........................................................................... -0. )...............................................................................................................± ...
Page 132
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 2.0 2.5 DS41202F-page 130 8 10 Frequency (MHz) ± 5% ± 2% ± 1% 3.0 3.5 4.0 4 AND TEMPERATURE DD 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 133
... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which V DD © 2007 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40°C ≤ T Unit Min Typ† ...
Page 134
... MHz OSC XT Oscillator mode MHz OSC XT Oscillator mode MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode kHz OSC LFINTOSC mode MHz OSC HFINTOSC mode MHz OSC HFINTOSC mode MHz OSC (3) EXTRC mode MHz OSC HS Oscillator mode © 2007 Microchip Technology Inc. ...
Page 135
... Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2007 Microchip Technology Inc. -40°C ≤ T ≤ +85°C for industrial A Min Typ† ...
Page 136
... Conditions Note WDT, BOR, Comparators, V and REF T1OSC disabled (1) WDT Current (1) BOR Current (1) Comparator Current , both comparators enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2007 Microchip Technology Inc. ...
Page 137
... Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. PIC16F684-I (Industrial) PIC16F684-E (Extended) Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 138
... Minimum operating MIN voltage ms Year Provided no other specifications are violated E/W -40°C ≤ T ≤ +85°C A E/W -40°C ≤ T ≤ +85°C A E/W +85°C ≤ T ≤ +125° Minimum operating MIN voltage V ms Year Provided no other specifications are violated © 2007 Microchip Technology Inc. ...
Page 139
... Ambient Temperature Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (P © 2007 Microchip Technology Inc. Typ Units 69.8 C/W 14-pin PDIP package 85.0 C/W 14-pin SOIC package 100 ...
Page 140
... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 15-3: LOAD CONDITIONS Load Condition Pin Legend for all pins for OSC2 output DS41202F-page 138 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance L © 2007 Microchip Technology Inc. ...
Page 141
... All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. © 2007 Microchip Technology Inc ...
Page 142
... A 2.0V ≤ V ≤ 5.5V, MHz DD -40°C ≤ T ≤ +85°C (Ind.), A -40°C ≤ T ≤ +125°C (Ext kHz μ 2.0V, -40°C to +85°C DD μ 3.0V, -40°C to +85°C DD μ 5.0V, -40°C to +85°C DD © 2007 Microchip Technology Inc. ...
Page 143
... These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. Fetch Read Q1 Q2 OS11 OS20 ...
Page 144
... Asserted low. FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS41202F-page 142 BOR 37 33 HYST (Device not in Brown-out Reset) © 2007 Microchip Technology Inc. ...
Page 145
... By design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 μF and 0.01 μF values in parallel are recommended. © 2007 Microchip Technology Inc. ≤ +125°C Min Typ† Max Units 2 — — ...
Page 146
... T — OSC 49 Max Units Conditions — ns — ns — ns — ns — prescale value (2, 4, ..., 256) — ns — ns — ns — ns — ns — ns — prescale value ( — ns — kHz 7 T — Timers in Sync OSC mode © 2007 Microchip Technology Inc. ...
Page 147
... CCP1 Input Period * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. CC01 CC02 CC03 ≤ +125°C ...
Page 148
... Max Units Comments ± 1.5)/ – 1 — dB 600 ns (NOTE 1) 1000 ns μ 1.5)/ mV. DD Units Comments V Low Range (VRR = 1) V High Range (VRR = 0) LSb Low Range (VRR = 1) LSb High Range (VRR = 0) Ω μs © 2007 Microchip Technology Inc. ...
Page 149
... ADC V is from external V REF 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. © 2007 Microchip Technology Inc. ≤ +125°C Min Typ† Max Units — ...
Page 150
... OSC REF ADCS<1:0> (ADRC mode 2. 5.0V DD Set GO/DONE bit to new data in A/D Result register If the A/D clock source is selected as RC, a time added before the CY A/D clock starts. This allows the SLEEP instruction to be executed. cycle. © 2007 Microchip Technology Inc. ...
Page 151
... T OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. © 2007 Microchip Technology Inc. ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the ...
Page 152
... PIC16F684 NOTES: DS41202F-page 150 © 2007 Microchip Technology Inc. ...
Page 153
... Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz © 2007 Microchip Technology Inc. vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC PIC16F684 5.5V 5 ...
Page 154
... EC Mode 6 MHz 8 MHz 10 MHz 12 MHz F OSC vs. F OVER V (HS MODE) OSC DD Typical IDD vs FOSC Over Vdd HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC 5.5V 5.0V 4.0V 3.0V 2.0V 14 MHz 16 MHz 18 MHz 20 MHz 5.5V 5.0V 4.5V 20 MHz © 2007 Microchip Technology Inc. ...
Page 155
... Typical: Statistical Mean @25°C 800 Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 700 600 500 400 300 200 100 0 2.0 2.5 © 2007 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD Maximum IDD vs FOSC Over Vdd HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs ...
Page 156
... DS41202F-page 154 vs. V OVER F (XT MODE) DD OSC XT Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD vs. V OVER F (EXTRC MODE) DD OSC EXTRC Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD 4.5 5.0 5.5 4.5 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 157
... OVER Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125° 2.0 2.5 © 2007 Microchip Technology Inc. vs. V OVER F (EXTRC MODE) DD OSC EXTRC Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ ...
Page 158
... DS41202F-page 156 (LP MODE) OSC LP Mode 32 kHz Maximum 32 kHz Typical 3.0 3.5 4.0 V (V) DD vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz F OSC 4.5 5.0 5.5 5.5V 5.0V 4.0V 3.0V 2.0V 4 MHz 8 MHz © 2007 Microchip Technology Inc. ...
Page 159
... Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 © 2007 Microchip Technology Inc. vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz F OSC vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) ...
Page 160
... MODE, ALL PERIPHERALS DISABLED) DD Maximum (Sleep Mode all Peripherals Disabled) Max. 125°C Max. 85°C 3.0 3.5 4.0 V (V) DD vs. V (BOTH COMPARATORS ENABLED Maximum Typical 3.0 3.5 4.0 V (V) DD 4.5 5.0 5.5 4.5 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 161
... Typical: Statistical Mean @25°C Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ 2.5 (-40°C to 125°C) 2.0 1.5 1.0 0.5 0.0 2.0 2.5 © 2007 Microchip Technology Inc. OVER TEMPERATURE DD Maximum Typical 3.5 4.0 4.5 V (V) DD vs. V OVER TEMPERATURE ...
Page 162
... Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Max. 85°C 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE DD Max. (125°C) Max. (85°C) Typical Minimum 3.0 3.5 4.0 V (V) DD 4.5 5.0 5.5 4.5 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 163
... Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ 120 (-40°C to 125°C) 100 2.0 2.5 © 2007 Microchip Technology Inc. (5.0V) DD Vdd = 5V Maximum Typical Minimum 25°C 85°C Temperature (°C) OVER TEMPERATURE (HIGH RANGE) DD High Range Max. 125°C Max. 85° ...
Page 164
... Max. 125°C Max. 85°C Typical 3.0 3.5 4 3.0V) DD (VDD = 3V, -40×C TO 125×C) Typical 25°C Min. -40°C 6.5 7.0 7.5 8.0 I (mA) OL 4.5 5.0 5.5 Max. 125°C Max. 85°C 8.5 9.0 9.5 10.0 © 2007 Microchip Technology Inc. ...
Page 165
... Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ 1.0 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 © 2007 Microchip Technology Inc. = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8.5 ...
Page 166
... I (mA) OH vs. V OVER TEMPERATURE IN DD (TTL Input, -40×C TO 125×C) Max. -40°C Typ. 25°C Min. 125°C 3.0 3.5 4.0 4.5 V (V) DD Max. -40°C Typ. 25°C Min. 125°C -4.0 -4.5 -5.0 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 167
... Maximum: Mean + 3 (-40×C to 125×C) (-40°C to 125°C) 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 2.0 2.5 © 2007 Microchip Technology Inc. vs (ST Input, -40×C TO 125×C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (32 kHz) DD Max. 125°C Max. 85°C Typ. 25° ...
Page 168
... V- input = Transition from V 400 300 200 100 0 2.0 DS41202F-page 166 + 100 2.5 4 100 2.5 4.0 V (V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 5.5 Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 5.5 © 2007 Microchip Technology Inc. ...
Page 169
... Microchip Technology Inc. OVER TEMPERATURE (31 kHz) DD LFINTOSC 31Khz Max. -40°C Typ. 25°C Min. 85°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 3 ...
Page 170
... Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD © 2007 Microchip Technology Inc. 5.0 5.5 5.0 5.5 ...
Page 171
... FIGURE 16-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2007 Microchip Technology Inc. OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 V (V) DD 3.0 3.5 4.0 4.5 V (V) ...
Page 172
... TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE 2.0 2.5 FIGURE 16-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41202F-page 170 3.0 3.5 4.0 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (85°C) DD 4.5 5.0 5.5 (125°C) DD 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 173
... FIGURE 16-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2007 Microchip Technology Inc. 3.0 3.5 4.0 4.5 V (V) DD PIC16F684 (-40°C) DD 5.0 5.5 DS41202F-page 171 ...
Page 174
... PIC16F684 NOTES: DS41202F-page 172 © 2007 Microchip Technology Inc. ...
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... Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2007 Microchip Technology Inc. PIC16F684 Example ...
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... E .290 E1 .240 D .735 L .115 c .008 b1 .045 b .014 eB – MAX 14 – .210 .130 .195 – – .310 .325 .250 .280 .750 .775 .130 .150 .010 .015 .060 .070 .018 .022 – .430 Microchip Technology Drawing C04-005B © 2007 Microchip Technology Inc. ...
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... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc ...
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... A1 0.05 – E 6.40 BSC E1 4.30 4.40 D 4.90 5.00 L 0.45 0.60 L1 1.00 REF φ 0° – c 0.09 – b 0.19 – Microchip Technology Drawing C04-087B φ L MAX 1.20 1.05 0.15 4.50 5.10 0.75 8° 0.20 0.30 © 2007 Microchip Technology Inc. ...
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... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc. EXPOSED PAD E2 2 ...
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... PIC16F684 NOTES: DS41202F-page 178 © 2007 Microchip Technology Inc. ...
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... Auto-Shutdown and Dead Band) Module” Revision E Updated Package Drawings; Replace PICmicro with PIC. Revision F (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section. © 2007 Microchip Technology Inc. PIC16F684 APPENDIX B: MIGRATING FROM OTHER PIC DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC16F6XX Family of devices ...
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... PIC16F684 NOTES: DS41202F-page 180 © 2007 Microchip Technology Inc. ...
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... MCLR Circuit............................................................. 100 On-Chip Reset Circuit ................................................. 99 PIC16F684.................................................................... 5 PWM (Enhanced)........................................................ 85 RA0 Pins ..................................................................... 35 RA1 Pins ..................................................................... 36 RA2 Pin....................................................................... 36 RA3 Pin....................................................................... 37 © 2007 Microchip Technology Inc. PIC16F684 RA4 Pin ...................................................................... 37 RA5 Pin ...................................................................... 38 RC0 and RC1 Pins ..................................................... 41 RC2 and RC3 Pins ..................................................... 41 RC4 Pin ...................................................................... 42 RC5 Pin ...................................................................... 42 Resonator Operation .................................................. 22 Timer1 ...
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... ANDLW..................................................................... 117 ANDWF..................................................................... 117 BCF .......................................................................... 117 BSF........................................................................... 117 BTFSC ...................................................................... 117 BTFSS ...................................................................... 118 CALL......................................................................... 118 CLRF ........................................................................ 118 CLRW ....................................................................... 118 CLRWDT .................................................................. 118 COMF ....................................................................... 118 DECF ........................................................................ 118 DECFSZ ................................................................... 119 GOTO ....................................................................... 119 INCF ......................................................................... 119 INCFSZ..................................................................... 119 IORLW ...................................................................... 119 IORWF...................................................................... 119 © 2007 Microchip Technology Inc. ...
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... MPLAB REAL ICE In-Circuit Emulator System................. 127 MPLINK Object Linker/MPLIB Object Librarian ................ 126 O OPCODE Field Descriptions ............................................. 115 OPTION Register .......................................................... 14, 45 OSCCON Register .............................................................. 20 Oscillator Associated registers.............................................. 30, 51 Oscillator Module ................................................................ 19 EC ............................................................................... 19 HFINTOSC.................................................................. 19 © 2007 Microchip Technology Inc. PIC16F684 HS............................................................................... 19 INTOSC ...................................................................... 19 INTOSCIO .................................................................. 19 LFINTOSC.................................................................. 19 LP ............................................................................... 19 RC .............................................................................. 19 RCIO........................................................................... 19 XT ............................................................................... 19 Oscillator Parameters ....................................................... 140 Oscillator Specifications ...
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... Reset, WDT, OST and Power-up Timer ................... 142 Time-out Sequence Case 1 .............................................................. 103 Case 2 .............................................................. 103 Case 3 .............................................................. 103 Timer0 and Timer1 External Clock ........................... 144 Two Speed Start-up.................................................... 28 Wake-up from Interrupt............................................. 113 Timing Parameter Symbology .......................................... 138 TRISA Register................................................................... 31 TRISC Register................................................................... 40 Two-Speed Clock Start-up Mode........................................ 27 © 2007 Microchip Technology Inc. ...
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... REF EE W Wake-up Using Interrupts ................................................. 112 Watchdog Timer (WDT) .................................................... 110 Associated Registers ................................................ 111 Clock Source............................................................. 110 Modes ....................................................................... 110 Period........................................................................ 110 Specifications............................................................ 143 WDTCON Register ........................................................... 111 WPUA Register ................................................................... 33 WWW Address.................................................................. 187 WWW, On-Line Support ....................................................... 4 © 2007 Microchip Technology Inc. PIC16F684 DS41202F-page 185 ...
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... PIC16F684 NOTES: DS41202F-page 186 © 2007 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41202F-page 188 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41202F © 2007 Microchip Technology Inc. ...
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... PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office PART NO. X /XX Device Temperature Package Range Device: PIC16F684, PIC16F684T V range 2.0V to 5.5V DD Temperature I = -40°C to +85°C Range -40°C to +125°C Package Quad Flat No Leads (QFN) ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...