PIC16F684T-E/ST Microchip Technology, PIC16F684T-E/ST Datasheet

no-image

PIC16F684T-E/ST

Manufacturer Part Number
PIC16F684T-E/ST
Description
IC PIC MCU FLASH 2KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F684T-E/ST

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
14-TSSOP
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F684T-E/ST
Quantity:
900
The PIC16F684 parts you have received conform
functionally to the Device Data Sheet (DS41202D),
except for the anomalies described below.
Microchip intends to address all issues listed here in
future revisions of the PIC16F684 silicon.
1. Module: Resets (when WDT times out)
2. Module: Data EEPROM Memory
© 2006 Microchip Technology Inc.
If the OPTION_REG bits, PS<2:0>, are clear,
multiple spurious Resets can occur when the WDT
times out. These Resets can occur even when the
PSA bit is clear, assigning the prescaler to the
Timer0.
Work around
If a CLRWDT instruction is issued before the WDT
times out and before the OPTION register is
modified, this problem is eliminated.
Date Codes that pertain to this issue:
All engineering and production devices.
The EEIF flag may be cleared inadvertently when
performing operations on the PIR1 register
simultaneously with the completion of an EEPROM
write. This condition occurs when the EEPROM
write timer completes at the same moment that the
PIR1 register operation is executed. Register
operations are those that have the PIR1 register as
the destination and include, but are not limited to,
BSF, BCF, ANDWF, IORWF and XORWF.
Work around
1. Avoid operations on the PIR1 register when
2. Poll the WR bit (EECON1<1>) to determine
3. Use a timer interrupt to catch any instances
writing to the EEPROM memory.
when the write is complete.
when the EEIF flag is inadvertently cleared.
The timer interrupt should be set longer than
8 ms. If EEIF fails, then the timer interrupt
occurs as a default time out. The WR and
WRERR flags are checked as part of the timer
interrupt service routine to verify the EEPROM
write success.
PIC16F684 Rev. A Silicon/Data Sheet Errata
3. Module: ECCP with Auto-Shutdown
4. If periodic interrupts are occurring in addition to
The PIC16F684 Rev. A4 silicon for the ECCP
Auto-Shutdown is connected to the C1IF and C2IF
flags. See Figures 8-2 and 8-3 on the following
page.
Rev. A4’s auto-shutdown connection to C1IF and
C2IF causes the auto-shutdown to incorrectly
operate synchronously. Additionally, reads of
CMCON0 will incorrectly clear an auto-shutdown
event.
Work around
Rev. A4 Silicon
1)
2)
3)
Fix
Rev. B2 Silicon
The Silicon Rev. B2 device (now shipping) has
moved the auto-shutdown connection from CxIF to
CxOUT. This will eliminate the synchronous
shutdown and simplify the use of the comparator
for a shutdown event. Figure 1 shows the function
of auto-shutdown before and after the device
revision.
the EEIF interrupts, then use a secondary flag
to sense write completion. The secondary flag
is set whenever EEPROM writes are active. An
EEPROM write completion is indicated when
the secondary flag is set and the WR flag is
clear.
PIC16F684
Poll the CxOUT bit until it is low.
Read CMCON1 to precondition CxIF.
If CMCON0 is read while CxOUT is changing,
repeat steps 1 and 2.
(Silicon Rev. A4 and B2)
DS80197E-page 1

Related parts for PIC16F684T-E/ST

PIC16F684T-E/ST Summary of contents

Page 1

... The WR and WRERR flags are checked as part of the timer interrupt service routine to verify the EEPROM write success. © 2006 Microchip Technology Inc. PIC16F684 4. If periodic interrupts are occurring in addition to the EEIF interrupts, then use a secondary flag to sense write completion ...

Page 2

... RD CMCON0 D Q Q3*RD CMCON0 EN CL Reset ). OSC To C1OUT pin Rev ECCP Auto-Shutdown To Data Bus Set C1IF bit Rev ECCP Auto-Shutdown To Timer1 Gate 0 To C2OUT pin 1 Rev ECCP Auto-Shutdown To Data Bus Set C2IF bit Rev ECCP Auto-Shutdown © 2006 Microchip Technology Inc. ...

Page 3

... FIGURE 1: SILICON REVISION A4 VS. REVISION B2 A4 CCP Output B2 CCP Output CxOUT CxIF Uncertainty due to Q1 cycle delay © 2006 Microchip Technology Inc. Read CMCON0 Uncertainty due to Q1 cycle delay PIC16F684 Read CMCON0 DS80197E-page 3 ...

Page 4

... Data Sheet Clarifications/Corrections Section: Added Module 2: New 4x4 QFN Package added. Rev E Document (7/2006) Added Module 3: ECCP with Auto-Shutdown (Silicon Rev. A4 and B2). Clarifications/Corrections to the Data Sheet: Removed Items 1 and 2, which have been incorporated into the data sheet. © 2006 Microchip Technology Inc. ...

Page 5

... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 6

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

Related keywords