PIC12F615-E/MF Microchip Technology, PIC12F615-E/MF Datasheet - Page 108
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12F615-E/MF
Manufacturer Part Number
PIC12F615-E/MF
Description
IC PIC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(26 pages)
3.PIC12F609T-ISN.pdf
(8 pages)
4.PIC12F615-EMF.pdf
(196 pages)
Specifications of PIC12F615-E/MF
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-DFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F615-EMF PDF datasheet #4
- Current page: 108 of 196
- Download datasheet (3Mb)
PIC12F609/615/12HV609/615
11.4.2
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
FIGURE 11-7:
DS41302B-page 106
(615 only)
(615 only)
(615 only)
TIMER0 INTERRUPT
IOC-GP0
IOC-GP1
IOC-GP2
IOC-GP3
IOC-GP4
IOC-GP5
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
ADIF
ADIE
CMIF
CMIE
INTERRUPT LOGIC
Note 1:
GPIE
GPIF
INTF
INTE
PEIE
T0IF
T0IE
GIE
Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 11.7.1 “Wake-up from Sleep”.
11.4.3
An input change on GPIO sets the GPIF bit of the
INTCON register. The interrupt can be enabled/
disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note:
GPIO INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
Wake-up (If in Sleep mode)
© 2008 Microchip Technology Inc.
Interrupt to CPU
(1)
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