PIC12F615-E/MF Microchip Technology, PIC12F615-E/MF Datasheet
PIC12F615-E/MF
Specifications of PIC12F615-E/MF
Related parts for PIC12F615-E/MF
PIC12F615-E/MF Summary of contents
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... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2008 Microchip Technology Inc. PIC12F609/12HV609 PIC12F615/12HV615 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41302B ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Option to use system clock as Timer1 TM • In-Circuit Serial Programming (ICSP pins PIC12F615/HV615 ONLY: • Enhanced Capture, Compare, PWM module: - 16-bit Capture, max. resolution 12 Compare, max. resolution 200 ns - 10-bit PWM with output channels, 1 output channel programmable “dead time”, max. frequency 20 kHz, auto-shutdown • ...
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... PIC12F609/615/12HV609/615 Program Memory Device Flash (words) PIC12F609 1024 PIC12HV609 1024 PIC12F615 1024 PIC12HV615 1024 8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN) GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/V TABLE 1: PIC12F609/HV609 PIN SUMMARY ( I/O Pin Comparators GP0 7 CIN+ GP1 6 CIN0- GP2 5 COUT (1) GP3 4 — GP4 ...
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... Diagram, PIC12F615/HV615 (PDIP, SOIC, MSOP, DFN) GP5/T1CKI/P1A*/OSC1/CLKIN GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT GP3/T1G*/MCLR/V * Alternate pin function. TABLE 2: PIC12F615/HV615 PIN SUMMARY ( I/O Pin Analog Comparators GP0 7 AN0 CIN+ GP1 6 AN1 CIN0- GP2 5 AN2 COUT (1) GP3 4 — — GP4 3 AN3 CIN1- GP5 2 — ...
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... Timer2 Module (PIC12F615/HV615 only) ................................................................................................................................. 52 8.0 Comparator Module .................................................................................................................................................................. 55 9.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/HV615 only) ...................................................................................... 67 10.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only) ...................... 77 11.0 Special Features of the CPU ..................................................................................................................................................... 95 12.0 Voltage Regulator ................................................................................................................................................................... 113 13.0 Instruction Set Summary ........................................................................................................................................................ 115 14.0 Development Support ............................................................................................................................................................ 125 15 ...
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... T1G T1CKI Timer0 T0CKI © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Block Diagrams and pinout descriptions of the devices are as follows: • PIC12F609/HV609 (Figure 1-1, Table 1-1) • PIC12F615/HV615 (Figure 1-2, Table 1-2) INT 13 Data Bus Program Counter RAM 8-Level Stack 64 Bytes File ...
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... PIC12F609/615/12HV609/615 FIGURE 1-2: PIC12F615/HV615 BLOCK DIAGRAM Configuration Flash Program Memory Program 14 Bus Instruction Reg Instruction Decode & Control OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator T1G* Block T1G T1CKI Timer0 T0CKI Analog-To-Digital Converter * Alternate pin function. DS41302B-page 6 INT 13 Data Bus Program Counter ...
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... GP5 T1CKI OSC1 CLKIN Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Input Output Type Type TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change AN — Comparator non-inverting input ST CMOS Serial Programming Data I/O ...
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... PIC12F609/615/12HV609/615 TABLE 1-2: PIC12F615/HV615 PINOUT DESCRIPTION Name Function GP0/AN0/CIN+/P1B/ICSPDAT ICSPDAT GP1/AN1/CIN0-/V /ICSPCLK REF ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A GP3/T1G*/MCLR/V PP GP4/AN3/CIN1-/T1G/P1B*/OSC2/ CLKOUT CLKOUT GP5/T1CKI/P1A*/OSC1/CLKIN Alternate pin function. Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL DS41302B-page 8 ...
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... Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory Wraps to 0000h-03FFh © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank ...
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... A0h General Purpose Registers 64 Bytes EFh F0h Accesses 70h-7Fh FFh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. DATA MEMORY MAP OF THE PIC12F615/HV615 File File Address Address (1) (1) Indirect Addr. 00h 80h OPTION_REG 01h 81h 02h PCL ...
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... Unimplemented Legend: – = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: Read only register. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO ...
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... PIC12F609/615/12HV609/615 TABLE 2-2: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. 4: TRISIO3 always reads as ‘1’ since input only pin. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 5 Bit 4 ...
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... PIC12F609/615/12HV609/615 TABLE 2-4: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 It is recommended, therefore, that only BCF, BSF, ...
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... PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) OSC 128 256 1 : 128 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... IOC register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. DS41302B-page 18 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...
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... Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note: Interrupt flag bits are set when an interrupt ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. DS41302B-page 20 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... P1BSEL: P1B Output Pin Select bit 1 = P1B function is on GP4/AN3/CIN1-/T1G/P1B 0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT bit 0 P1ASEL: P1A Output Pin Select bit 1 = P1A function is on GP5/T1CKI/P1A 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A Note 1: PIC12F615/HV615 only. 2: Alternate pin function. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 (1) R/W-0 U-0 ...
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... Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE INDIRECT ADDRESSING 0x40 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,7 ;all done? NEXT ;no clear next ;yes continue © 2008 Microchip Technology Inc. ...
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... Bank 0 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in this area are mirrored back into Bank 0 and Bank 1. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 0 IRP Bank Select ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 24 © 2008 Microchip Technology Inc. ...
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... PIC MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator OSC2 Sleep OSC1 Internal Oscillator INTOSC 8 MHz © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode. 3. ...
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... These oscillator delays are shown in Table 3-1. Frequency Oscillator Delay 125 kHz to 8 MHz Oscillator Warm-Up Delay (T DC – 20 MHz 2 instruction cycles 32 kHz to 20 MHz 1024 Clock Cycles (OST) (1) ) WARM © 2008 Microchip Technology Inc. ...
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... The value of R varies with the Oscillator mode F selected (typically between 2 MΩ MΩ). © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...
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... The CLKOUT Internal signal may be used to provide a clock for external Clock circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. ) values EXT See Section 11.0 “Special © 2008 Microchip Technology Inc. ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 11-1) for operation of all register bits. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 30 © 2008 Microchip Technology Inc. ...
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... Note 1: TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘0’ when MCLRE = 1. ...
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... Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. Note change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. © 2008 Microchip Technology Inc. ...
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... Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 4-4: ANSEL: ANALOG SELECT REGISTER (PIC12F615/HV615) U-0 R/W-1 R/W-1 — ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 IOC4 IOC3 IOC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 WPU1 WPU0 bit Bit is unknown R/W-0 R/W-0 IOC1 IOC0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Figure 4-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • an analog inverting input to the comparator • a voltage reference input for the ADC (1) /ICSPDAT • In-Circuit Serial Programming clock Note 1: PIC12F615/HV615 only. Analog Input Mode ...
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... IOC RD IOC ( Interrupt-on- From other Change R GP<5:3, 1:0> pins Write ‘0’ to GBIF Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC12F615/HV615 only. DS41302B-page 36 (1) / Note 1: PIC12F615/HV615 only. (1) Analog Input Mode C1OE Enable C1OE (1) Analog ...
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... Figure 4-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • a Timer1 gate (count enable), alternate pin • as Master Clear Reset with weak pull-up Note 1: Alternate pin function. 2: PIC12F615/HV615 only. FIGURE 4-3: BLOCK DIAGRAM OF GP3 Data Bus RD TRISIO ...
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... Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC12F615/HV615 only. DS41302B-page 38 • PWM output, alternate pin • a crystal/resonator connection • a clock output Note 1: Alternate pin function. 2: PIC12F615/HV615 only. (3) Analog Input Mode CLK Modes ...
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... FIGURE 4-5: BLOCK DIAGRAM OF GP5 ( Interrupt-on- Change R Write ‘0’ to GBIF Note 1: Timer1 LP Oscillator enabled. 2: Set has priority over Reset. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Note 1: Alternate pin function. 2: PIC12F615/HV615 only. INTOSC Mode Data Bus WPU GPPU RD WPU Oscillator Circuit ...
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... TICKPS1 (1) CCP1CON P1M — DC1B1 (1) APFCON — — — Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO. Note 1: PIC12F615/HV615 only. DS41302B-page 40 Bit 4 Bit 3 Bit 2 Bit 1 (1) (1) (1) ADCS0 ANS3 ANS2 ANS1 CMPOL — CMR — ...
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... WDTE Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...
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... T0CKI input and the Timer0 register is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements Section 15.0 “Electrical Specifications”. © 2008 Microchip Technology Inc. as shown in ...
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... TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 44 © 2008 Microchip Technology Inc. ...
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... When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 6.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source ...
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... GP3/T1G Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: Alternate pin function. 5: PIC12F615/HV615 only. DS41302B-page 46 TMR1ON To Comparator Module Timer1 Clock ( TMR1L 1 (1) T1SYNC ...
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... Note: In asynchronous counter mode or when using the internal oscillator and T1ACS=1, Timer1 can not be used as a time base for the capture or compare modes of the ECCP module (for PIC12F615/HV615 only). 6.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...
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... In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 10.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only)”. © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC12F609/615/12HV609/615 For more information, see Section 10.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only)”. 6.11 Comparator Synchronization The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module ...
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... Timer1 gate source. 3: See T1ACS bit in CMCON1 register. DS41302B-page 50 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) /4) or system clock (F ) OSC R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC12F615/HV615 only. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 4 Bit 3 Bit 2 Bit 1 T1GSEL — ...
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... PIC12F609/615/12HV609/615 7.0 TIMER2 MODULE (PIC12F615/HV615 ONLY) The Timer2 module is an 8-bit timer with the following features: • 8-bit timer register (TMR2) • 8-bit period register (PR2) • Interrupt on TMR2 match with PR2 • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) See Figure 7-1 for a block diagram of Timer2 ...
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... T2CON — TOUTPS3 TOUTPS2 Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note 1: For PIC12F615/HV615 only. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-0 R/W-0 TOUTPS1 TOUTPS0 TMR2ON U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 54 © 2008 Microchip Technology Inc. ...
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... REF MUX CV REF 1 CMV REN Note © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 than the analog voltage at V parator is a digital low level. When the analog voltage greater than the analog voltage output of the comparator is a digital high level. FIGURE 8-1:SINGLE COMPARATOR V + ...
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... The analog SS and the 2: Analog levels on any pin defined as a dig- DD ital input, may cause the input buffer to consume more current than is specified ≈ 0. LEAKAGE ≈ 0. ±500 Comparator © 2008 Microchip Technology Inc. ...
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... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 8.3.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register ...
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... Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before comparator interrupts. © 2008 Microchip Technology Inc. reset by software from the enabling ...
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... INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.7 Effects of a Reset A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 DS41302B-page 59 ...
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... Comparator output requires the following three conditions: CMOE = 1, CMON = 1 and corresponding port TRIS bit = 0. DS41302B-page 60 R/W-0 U-0 CMPOL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > CMV - < CMV - > CMV - < CMV - IN IN (1) output REF R/W-0 U-0 R/W-0 CMR — CMCH bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. 2: Refer to Figure 8-2. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 8.9 Synchronizing Comparator Output to Timer1 The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register ...
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... When the CMVREN bit is cleared, current flow in the CV voltage divider is disabled minimizing the power REF drain of the voltage reference peripheral. SS module current. REF derived and DD output changes with fluctuations in REF , with DD or fixed REF voltage divider REF voltage for use by the Compar- REF © 2008 Microchip Technology Inc. ...
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... COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CMVREN (1) CV REF To Comparators and ADC Module FixedRef To Comparators and ADC Module Note 1: Care should be taken to ensure CV Section 15.0 “Electrical Specifications” for more detail. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 16 Stages Analog MUX 15 0 (1) VR<3:0> 0.6V ...
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... Comparator REF input of the Comparator REF (2) Value Selection bits (0 ≤ VR<3:0> ≤ 15) REF = (VR<3:0>/24 (VR<3:0>/32 circuit is powered down and does not contribute to I REF R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown current. DD © 2008 Microchip Technology Inc. ...
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... Hysteresis) Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Figure 8-7 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis ...
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... TRISIO — — TRISIO5 VRCON CMVREN — VRR Legend: = unknown, = unchanged, = unimplemented, read as ‘0’. Shaded cells are not used for comparator. Note 1: For PIC12F615/HV615 only. DS41302B-page 66 Bit 4 Bit 3 Bit 2 Bit 1 (1) (1) (1) ADCS0 ANS3 ANS2 ANS1 CMPOL — CMR — ...
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... ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC12F615/HV615 ONLY) The Analog-to-Digital Converter conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter ...
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... Section 15.0 “Electrical Specifications” for more information. Table 9-1 gives examples of appropriate ADC clock selections. Note: Unless using the F , any changes in the RC system clock frequency will change the ADC clock frequency, adversely affect the ADC result. © 2008 Microchip Technology Inc. periods AD specification AD which may ...
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... Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 9.1.5 “Interrupts” for more information. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 ) V . DEVICE OPERATING FREQUENCIES (VDD > 3.0V ...
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... Using the Special Event Trigger does not assure proper ADC timing the user’s responsibility to ensure that the ADC timing requirements are met. See Section 10.0 “Enhanced Capture/Compare/ PWM (With Auto-Shutdown and Dead Band) Mod- ule (PIC12F615/HV615 only)” for more information. ADRESL bit 0 Unimplemented: Read as ‘0’ LSB ...
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... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 9.3 “A/D Requirements”. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 EXAMPLE 9-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ; ...
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... If the Comparator module uses this 0.6V reference voltage, the comparator output may momentarily change state due to the transient. DS41302B-page 72 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 R-x R-x R-x ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ ...
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... HOLD Ω 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED © 2008 Microchip Technology Inc. ...
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... R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h 003h 002h 001h 000h REF © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 V DD Sampling Switch V = 0.6V T ≤ Rss LEAKAGE V = 0.6V T ± 500 ...
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... CCP1IE (1) PIR1 — ADIF CCP1IF TRISIO — — TRISIO5 Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note 1: For PIC12F615/HV615 only. 2: Read Only Register. DS41302B-page 76 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE (1) ...
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... ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTO- SHUTDOWN AND DEAD BAND) MODULE (PIC12F615/HV615 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The Compare mode allows the user to trigger an external ...
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... NEW_CAPT_PS ;Load the W reg with CCPR1L MOVWF CCP1CON TMR1L of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value © 2008 Microchip Technology Inc. ...
Page 81
... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture. Note 1: For PIC12F615/HV615 only. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 4 Bit 3 Bit 2 Bit 1 ...
Page 82
... CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. the match condition by © 2008 Microchip Technology Inc. ...
Page 83
... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR2 Timer2 Module Register TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Compare. Note 1: For PIC12F615/HV615 only. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 ...
Page 84
... In PWM mode, CCPR1H is a read-only register. DS41302B-page 82 The PWM output (Figure 10-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 10-4: Period Pulse Width TMR2 = 0 CCP1 TRIS ), or OSC CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPRxL:CCPxCON<5:4> © 2008 Microchip Technology Inc. ...
Page 85
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 EQUATION 10-2: Pulse Width EQUATION 10-3: • OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle ...
Page 86
... T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output driver by clear- ing the associated TRIS bit. © 2008 Microchip Technology Inc. ...
Page 87
... EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode Single Half-Bridge © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately ...
Page 88
... Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.5 “Programmable Dead-Band Delay mode”). P1D Modulated DS41302B-page 86 Pulse 0 Width Period (1) (1) Delay Delay Pulse 0 Width Period (1) (1) Delay Delay © 2008 Microchip Technology Inc. PR2+1 PR2+1 ...
Page 89
... Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit P1A P1B © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. ...
Page 90
... Output mode and complete a full PWM cycle before configuring the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41302B-page 88 © 2008 Microchip Technology Inc. ...
Page 91
... From Comparator 001 000 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state ...
Page 92
... PWM signal will always restart at the beginning of the next PWM period. DS41302B-page 90 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) condition R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 93
... ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 10-12: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Period Shutdown Shutdown Event Occurs ...
Page 94
... P1B ( Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high OSC V+ FET Driver P1A Load FET Driver P1B V- EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period Period td (1) ( © 2008 Microchip Technology Inc. ...
Page 95
... Timer2 Module Register TRISIO — — TRISIO5 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the PWM. Note 1: For PIC12F615/HV615 only. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ...
Page 96
... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 94 © 2008 Microchip Technology Inc. ...
Page 97
... The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 11-1). © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 11.1 Configuration Bits The Configuration bits can be programmed (read as ‘ ...
Page 98
... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41302B-page 96 — — (3) PWRTE WDTE FOSC2 P = Programmable’ ‘0’ = Bit is cleared (1) (2) (3) (1) (1) — BOREN1 BOREN0 bit 8 FOSC1 FOSC0 bit Unimplemented bit, read as ‘0’ Bit is unknown DD © 2008 Microchip Technology Inc. ...
Page 99
... CLKIN pin PWRT On-Chip 11-bit Ripple Counter RC OSC Note 1: Refer to the Configuration Word register (Register 11-1). © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 • Power-on Reset • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation ...
Page 100
... V RECOMMENDED MCLR CIRCUIT DD ® PIC R1 MCU 1 kΩ (or greater) R2 MCLR 100 Ω (needed with capacitor) C1 0.1 μF (optional, not critical) for details (Section 15.0 at the MCLR SS Ω should be used when . SS © 2008 Microchip Technology Inc. ...
Page 101
... Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until V above V (see Figure 11-3). If enabled, the Power- BOR up Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms ...
Page 102
... Bit 2 Bit 1 — — — POR may have gone too DD Wake-up from Sleep PWRTE = 1 1024 • T 1024 • T OSC OSC — — Value on Value on Bit 0 all other POR, BOR (1) Resets BOR ---- --qq ---- --uu C 0001 1xxx 000q quuu © 2008 Microchip Technology Inc. ...
Page 103
... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 T PWRT T PWRT T PWRT T OST T OST ) DD T OST DS41302B-page 101 ...
Page 104
... Microchip Technology Inc. Interrupt uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu ---u uuuu (2) uuuu uuuu (2) ...
Page 105
... TABLE 11-5: INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/HV615) Register Address Power-on Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx GPIO 05h --x0 x000 PCLATH 0Ah/8Ah ---0 0000 INTCON ...
Page 106
... DS41302B-page 104 Program Status Counter Register 000h 0001 1xxx 000h 000u uuuu 000h 0001 0uuu 000h 0000 uuuu uuu0 0uuu 000h 0001 1uuu ( uuu1 0uuu © 2008 Microchip Technology Inc. PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu ...
Page 107
... Comparator Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • Enhanced CCP Interrupt © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 11-8) ...
Page 108
... Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 11.7.1 “Wake-up from Sleep”. (1) Wake-up (If in Sleep mode) Interrupt to CPU © 2008 Microchip Technology Inc. ...
Page 109
... PIR1 — ADIF CCP1IF (1) (1) PIE1 — ADIE CCP1IE Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC12F615/HV615 only. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 (1) (2) Interrupt Latency ...
Page 110
... The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. as clear The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out. © 2008 Microchip Technology Inc. ...
Page 111
... Bit 5 OPTION_REG GPPU INTEDG T0CS CONFIG IOSCFS CP MCLRE Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 11-1 for operation of all Configuration Word register bits. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 1 0 8-bit Prescaler PSA PS<2:0> 0 PSA Bit 4 ...
Page 112
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 11-9 for more details. © 2008 Microchip Technology Inc. ...
Page 113
... ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 OST (2) T (3) ...
Page 114
... GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 11-10. FIGURE 11-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector * PIC12F615/12HV615 Signals PIC12F609/12HV609 + MCLR/V PP GP1 CLK Data I/O ...
Page 115
... See Figure 12-1 for voltage regulator schematic. FIGURE 12-1: VOLTAGE REGULATOR V UNREG R I SER SUPPLY I SHUNT C Feedback BYPASS Device © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 An external current limiting resistor, R between the unregulated supply, V pin, drops the difference in voltage between V and SER defined by Equation 12- EQUATION 12-1: supply current R ...
Page 116
... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 114 © 2008 Microchip Technology Inc. ...
Page 117
... For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended conse- quence of clearing the condition that set the GPIF flag. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 TABLE 13-1: OPCODE FIELD ...
Page 118
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2008 Microchip Technology Inc. ...
Page 119
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 BCF Syntax: k Operands: Operation: Status Affected: ...
Page 120
... Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2008 Microchip Technology Inc. ...
Page 121
... Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 INCFSZ Syntax: Operands: Operation: Status Affected: Description: ...
Page 122
... Move label ] MOVWF f 0 ≤ f ≤ 127 (W) → (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP © 2008 Microchip Technology Inc. ...
Page 123
... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 RETLW Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: TABLE DONE RETURN Syntax: Operands: ...
Page 124
... Subtract W from literal [ label ] SUBLW k 0 ≤ k ≤ 255 k - (W) → (W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. Result Condition W > ≤ W<3:0> > k<3:0> W<3:0> ≤ k<3:0> © 2008 Microchip Technology Inc. ...
Page 125
... Operation: Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF f,d 0 ≤ ...
Page 126
... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 124 © 2008 Microchip Technology Inc. ...
Page 127
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 128
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2008 Microchip Technology Inc. ...
Page 129
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 130
... Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® battery management, SEEVAL © 2008 Microchip Technology Inc. ...
Page 131
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 ........................................................................... -0. )...............................................................................................................± ...
Page 132
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH, ≤ ≤ -40°C T +125°C A 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41302B-page 130 8 10 Frequency (MHz Frequency (MHz © 2008 Microchip Technology Inc. ...
Page 133
... Note 1: This is the limit to which User defined. Voltage across the shunt regulator should not exceed 5V. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40°C ≤ T Min Typ† Max Units 2.0 — ...
Page 134
... OSC LP Oscillator mode MHz OSC XT Oscillator mode MHz OSC XT Oscillator mode MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode MHz OSC INTOSC mode MHz OSC INTOSC mode MHz OSC (3) EXTRC mode MHz OSC HS Oscillator mode © 2008 Microchip Technology Inc. ...
Page 135
... For RC oscillator configurations, current through R be extended by the formula I © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 -40°C ≤ T ≤ +85°C for industrial A -40°C ≤ T ≤ ...
Page 136
... T1OSC disabled 40°C ≤ T ≤ +25°C for industrial - A (1) WDT Current (1) BOR Current (1) Comparator Current , single comparator enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2008 Microchip Technology Inc. ...
Page 137
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ≤ ...
Page 138
... Conditions Note WDT, BOR, Comparator, V and REF T1OSC disabled (1) WDT Current (1) BOR Current (1) Comparator Current , single comparator enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2008 Microchip Technology Inc. ...
Page 139
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied Shunt regulator is always on and always draws operating current. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 -E (Extended) -40°C ≤ T ≤ ...
Page 140
... V ≤ PIN DD μA ≤ V ≤ XT, HS and SS PIN DD LP oscillator configuration μ 5.0V PIN 7.0 mA 4.5V -40°C to +125° 8.5 mA 4.5V -40°C to +85° -2.5mA 4.5V -40°C to +125° -3.0 mA 4.5V -40°C to +85°C © 2008 Microchip Technology Inc. ...
Page 141
... This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled. 5: This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) -40° ...
Page 142
... PDIP package 39.9* C/W 8-pin SOIC package 39* C/W 8-pin MSOP package 9* C/W 8-pin DFN 3x3mm package 3.0* C/W 8-pin DFN 4x4mm package 150* C — INTERNAL — INTERNAL DD (NOTE 1) = Σ Σ (I — — DER MAX DIE (NOTE 2) © 2008 Microchip Technology Inc )/θ ...
Page 143
... I/O Port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 15-3: LOAD CONDITIONS Load Condition Pin Legend for all pins for OSC2 output © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise ...
Page 144
... LP Oscillator mode ns XT Oscillator mode ns HS Oscillator mode ns EC Oscillator mode μs LP Oscillator mode ns XT Oscillator mode ns HS Oscillator mode ns RC Oscillator mode 4/F CY OSC μs LP oscillator ns XT oscillator ns HS oscillator ns LP oscillator ns XT oscillator ns HS oscillator © 2008 Microchip Technology Inc. ...
Page 145
... When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices ensure these oscillator frequency tolerances, V possible. 0.1 μF and 0.01 μF values in parallel are recommended design. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Freq. Min Typ† Max Tolerance — ...
Page 146
... OSC — — ↑ (Q2 cycle) 20 — OSC (2) — 15 — 40 (2) — 28 — — T — CY OSC Execute Q3 OS12 OS18 New Value Max Units Conditions 5. 5. — 5.0V DD — 5.0V DD — 5.0V DD — ns — © 2008 Microchip Technology Inc. ...
Page 147
... Note 1: Asserted low. FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 BOR 37 33 HYST (Device not in Brown-out Reset) ...
Page 148
... All specified values and V must be capacitively decoupled as close to the device Conditions μ 5V, -40°C to +85°C DD μ 5V, -40°C to +125° 5V, -40°C to +85° 5V, -40°C to +125° (NOTE 3) OSC ms μs V (NOTE 4) mV μs ≤ BOR © 2008 Microchip Technology Inc. ...
Page 149
... Delay from External Clock Edge to Timer TMR Increment * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Min Typ† ...
Page 150
... PIC12F609/615/12HV609/615 FIGURE 15-9: PIC12F615/HV615 CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) Note: Refer to Figure 15-3 for load conditions. TABLE 15-6: PIC12F615/HV615 CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating Temperature A Param Sym Characteristic No. CC01* TccL CCP1 Input Low Time ...
Page 151
... VP6 VP6 voltage output OUT VR02 V1P2 V1P2 voltage output OUT VR03* T Settling Time STABLE * These parameters are characterized but not tested. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 ≤ +125°C Min Typ† ± 5.0 (2) — 0 — +55 — Falling — ...
Page 152
... Settling Time SETTLE SR04 C Load Capacitance LOAD ΔI SR05 Regulator operating current SNT * These parameters are characterized but not tested. TABLE 15-11: PIC12F615/HV615 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature A Param Sym Characteristic No. AD01 N Resolution ...
Page 153
... TABLE 15-12: PIC12F615/HV615 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature A Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T Amplifier Settling Time ...
Page 154
... OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. FIGURE 15-11: PIC12F615/HV615 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 ( OSC Q4 A/D CLK A/D Data ADRES ADIF GO ...
Page 155
... Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125° FIGURE 16-2: PIC12F609/615 I 600 Typical: Statistical Mean @25°C 500 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 400 300 200 100 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 LP (32 kHz MHz) vs (V) DD Maximum Typical 5 6 Maximum ...
Page 156
... PIC12F609/615 I 1200 Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 600 400 200 0 1 DS41302B-page 154 EC (4 MHz MHz MHz) vs (V) DD Maximum Typical 5 6 Maximum Typical 5 6 Maximum Typical 5 6 © 2008 Microchip Technology Inc. ...
Page 157
... FIGURE 16-7: PIC12F609/615 I 1800 Typical: Statistical Mean @25°C 1600 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1400 1200 1000 800 600 400 200 0 1 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 INTOSC (4 MHz) vs (V) DD INTOSC (8 MHz) vs (V) DD Maximum Typical ...
Page 158
... FIGURE 16-9: PIC12F609/615 I Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) DS41302B-page 156 EXTRC (4 MHz (20 MHz) vs Maximum Typical 6 5 Maximum Typical (V) DD © 2008 Microchip Technology Inc. ...
Page 159
... Extended: Mean (Worst-Case Temp) + 3σ 7 (-40°C to 125° FIGURE 16-11: PIC12F609/615 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 BASE vs (V) DD COMPARATOR (SINGLE ON) vs Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125° (V) DD Extended ...
Page 160
... PIC12F609/615 I 20 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp (-40°C to 85°C) Extended: Mean (Worst-Case Temp (-40°C to 125° DS41302B-page 158 WDT vs (V) DD BOR vs σ σ (V) DD Extended Industrial Typical 6 5 Extended Industrial Typical 5 6 © 2008 Microchip Technology Inc. ...
Page 161
... FIGURE 16-15: PIC12F609/615 I 120 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp 100 (-40°C to 85°C) Extended: Mean (Worst-Case Temp (-40°C to 125° © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 CV (LOW RANGE) vs REF DD σ σ ( (HI RANGE) vs REF DD σ σ VDD (V) Maximum ...
Page 162
... Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 20 (-40°C to 125° FIGURE 16-17: PIC12F615 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ 12 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 10 (-40°C to 125° ...
Page 163
... FIGURE 16-20: PIC12HV609/615 I 1400 Typical: Statistical Mean @25°C 1200 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1000 800 600 400 200 0 1 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 LP (32 kHz MHz MHz) vs ...
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... Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 600 400 200 0 1 DS41302B-page 162 XT (1 MHz MHz) vs (V) DD INTOSC (4 MHz) vs (V) DD Maximum Typical 5 4 Maximum Typical 5 4 Maximum Typical 5 4 © 2008 Microchip Technology Inc. ...
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... FIGURE 16-26: PIC12HV609/615 I 400 Typical: Statistical Mean @25°C 350 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 300 250 200 150 100 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 INTOSC (8 MHz) vs (V) DD EXTRC (4 MHz) vs (V) DD BASE vs ...
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... Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 350 (-40°C to 125°C) 300 250 200 150 100 2 DS41302B-page 164 COMPARATOR (SINGLE ON) vs (V) DD WDT vs (V) DD BOR vs ( Maximum Typical 5 4 Maximum Typical 5 4 Maximum Typical 4 5 © 2008 Microchip Technology Inc. ...
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... FIGURE 16-32: PIC12HV609/615 I Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 350 300 250 200 150 100 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 CV (LOW RANGE) vs REF ( (HI RANGE) vs REF (V) DD T1OSC vs ...
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... DS41302B-page 166 A 3.0V) DD 6.5 7.0 7.5 8.0 I (mA) OL Maximum Typical 4 5 Max. 125°C Max. 85°C Typical 25°C Min. -40°C 8.5 9.0 9.5 10.0 © 2008 Microchip Technology Inc. ...
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... Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 1.0 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8 ...
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... DS41302B-page 168 = 5.0V) DD -1.5 -2.0 -2.5 -3.0 -3.5 I (mA) OH vs. V OVER TEMPERATURE IN DD Max. -40°C Typ. 25°C Min. 125°C 3.0 3.5 4.0 4.5 V (V) DD Max. -40°C Typ. 25°C Min. 125°C -4.0 -4.5 -5.0 5.0 5.5 © 2008 Microchip Technology Inc. ...
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... FIGURE 16-40: TYPICAL HFINTOSC START-UP TIMES vs 85°C 12 25°C 10 -40° 2.0 2.5 3.0 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 vs 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 ...
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... Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD © 2008 Microchip Technology Inc. 5.0 5.5 5.0 5.5 ...
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... FIGURE 16-43: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 16-44: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 V (V) DD (25°C) DD 5.0 5.5 (85°C) DD 4.5 5.0 5.5 DS41302B-page 171 ...
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... PIC12F609/615/12HV609/615 FIGURE 16-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 16-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41302B-page 172 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (125°C) DD 5.0 5.5 (-40°C) DD 5.0 5.5 © 2008 Microchip Technology Inc. ...
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... REFERENCE VOLTAGE vs. TEMP (TYPICAL) 1.26 1.25 1.24 1.23 1.22 1.21 1.2 -60 -40 -20 FIGURE 16-49: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.16 5.14 5.12 5.1 5.08 5.06 5.04 5.02 5 4.98 4. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Temp ( Temp ( Input Current (mA) 2. 5.5V 100 120 140 2 ...
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... V- input = Transition from V 500 400 300 200 100 0 2.0 DS41302B-page 174 Temp (C) + 100mV 20mV CM CM 2.5 4.0 V (V) DD 4mA 10mA 15mA 20mA 40mA 50mA 100 120 140 Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 5.5 © 2008 Microchip Technology Inc. ...
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... V+ input = V CM 500 V- input = Transition from V 400 300 200 100 0 2.0 FIGURE 16-53: WDT TIME-OUT PERIOD vs 1.5 2 © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 - 100mV 2.5 4.0 V (V) DD OVER TEMPERATURE DD 2 (V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 5.5 125° ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 176 © 2008 Microchip Technology Inc. ...
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... Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 Example ...
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... PIC12F609/615/12HV609/615 17.2 Package Details The following sections give the technical details of the packages. DS41302B-page 178 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC12F609/615/12HV609/615 φ α β DS41302B-page 179 ...
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... PIC12F609/615/12HV609/615 DS41302B-page 180 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC12F609/615/12HV609/615 I φ DS41302B-page 181 ...
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... PIC12F609/615/12HV609/615 DS41302B-page 182 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC12F609/615/12HV609/615 DS41302B-page 183 ...
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... PIC12F609/615/12HV609/615 DS41302B-page 184 © 2008 Microchip Technology Inc. ...
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... Revision A This is a new data sheet. Revision B (05/2008) Added Graphs. Revised 28-Pin ICD Pinout, Electrical Specifications Section, Package Details. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 APPENDIX B: This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX Family of devices. B.1 ...
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... PIC12F609/615/12HV609/615 NOTES: DS41302B-page 186 © 2008 Microchip Technology Inc. ...
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... Reference Voltage (V )........................................... 68 REF Result Formatting........................................................ 70 Source Impedance...................................................... 74 Special Event Trigger.................................................. 70 Starting an A/D Conversion ........................................ 70 ADC (PIC12F615/HV615 Only) .......................................... 67 ADCON0 Register............................................................... 72 ADRESH Register (ADFM = 0) ........................................... 73 ADRESH Register (ADFM = 1) ........................................... 73 ADRESL Register (ADFM = 0)............................................ 73 ADRESL Register (ADFM = 1)............................................ 73 Analog Input Connection Considerations............................ 56 Analog-to-Digital Converter. See ADC ANSEL Register (PIC12F609/HV609) ...
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... Output Relationships (Active-High and Active-Low) ................................................. 86 Output Relationships Diagram ............................ 86 Programmable Dead Band Delay ....................... 92 Shoot-through Current ........................................ 92 Start-up Considerations ...................................... 88 Specifications ............................................................ 148 Timer Resources......................................................... 77 Enhanced Capture/Compare/PWM (PIC12F615/HV615 Only) ........................................... 77 Errata .................................................................................... 4 DS41302B-page 188 F Firmware Instructions ....................................................... 115 Fuses. See Configuration Bits G General Purpose Register File ............................................. 9 GPIO................................................................................... 31 Additional Pin Functions ............................................. 32 ANSEL Register ...
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... PCL and PCLATH............................................................... 22 Stack........................................................................... 22 PCON Register ........................................................... 20, 100 PICSTART Plus Development Programmer..................... 128 PIE1 Register ..................................................................... 18 Pin Diagram PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)........... 2 PIC12F615/HV615 (PDIP, SOIC, MSOP, DFN)........... 3 Pinout Descriptions PIC12F609/12HV609 ................................................... 7 PIC12F615/12HV615 ................................................... 8 PIR1 Register ..................................................................... 19 Power-Down Mode (Sleep)............................................... 110 Power-on Reset (POR)....................................................... 98 Power-up Timer (PWRT) .................................................... 98 Specifications ...
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... Specifications ............................................................ 147 T0CKI .......................................................................... 42 Timer1 ................................................................................. 45 Associated registers.................................................... 51 Asynchronous Counter Mode ..................................... 47 Reading and Writing ........................................... 47 Comparator Synchronization ...................................... 49 ECCP Special Event Trigger (PIC12F615/HV515 Only) ................................... 49 ECCP Time Base (PIC12F615/HV515 Only) .............. 48 Interrupt....................................................................... 48 Modes of Operation .................................................... 45 Operation During Sleep .............................................. 48 Oscillator ..................................................................... 47 Prescaler ..................................................................... 47 Specifications ............................................................ 147 Timer1 Gate Inverting Gate ..................................................... 48 Selecting Source........................................... 48, 61 Synchronizing COUT w/Timer1 ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41302B-page 192 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41302B © 2008 Microchip Technology Inc. ...
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... Pattern: QTP, SQTP or ROM Code; Special Requirements (blank otherwise) © 2008 Microchip Technology Inc. PIC12F609/615/12HV609/615 XXX Examples: Pattern a) PIC12F615-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC12F615-I/SN = Industrial Temp., SOIC package, 20 MHz c) PIC12F615T-E/MF Tape and Reel, Extended (1) (1) , PIC12HV609, PIC12HV609T , Temp ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...