C8051F017R Silicon Laboratories Inc, C8051F017R Datasheet - Page 82

IC 8051 MCU 32K FLASH 32LQFP

C8051F017R

Manufacturer Part Number
C8051F017R
Description
IC 8051 MCU 32K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F01xr
Datasheets

Specifications of C8051F017R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1042-2
Q1057388

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F017R
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
EXVLD
R/W
Bit7
This bit sets the masking of the XTLVLD interrupt.
0: Disable all XTLVLD interrupts.
1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7)
This bit sets the masking of External Interrupt 7.
0: Disable External Interrupt 7.
1: Enable interrupt requests generated by the External Interrupt 7 input pin.
This bit sets the masking of External Interrupt 6.
0: Disable External Interrupt 6.
1: Enable interrupt requests generated by the External Interrupt 6 input pin.
This bit sets the masking of External Interrupt 5.
0: Disable External Interrupt 5.
1: Enable interrupt requests generated by the External Interrupt 5 input pin.
This bit sets the masking of External Interrupt 4.
0: Disable External Interrupt 4.
1: Enable interrupt requests generated by the External Interrupt 4 input pin.
EADC0: Enable ADC0 End of Conversion Interrupt.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt.
1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable all Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3 flag (TMR3CN.7)
EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt.
Reserved. Must Write 0. Reads 0.
EX7: Enable External Interrupt 7.
EX6: Enable External Interrupt 6.
EX5: Enable External Interrupt 5.
EX4: Enable External Interrupt 4.
ET3: Enable Timer 3 Interrupt.
R/W
Bit6
-
Figure 10.12. EIE2: Extended Interrupt Enable 2
EX7
R/W
Bit5
EX6
R/W
Bit4
Rev. 1.7
EX5
R/W
Bit3
EX4
R/W
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
EADC0
R/W
Bit1
R/W
ET3
Bit0
SFR Address:
Reset Value
00000000
0xE7
82

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