HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 94

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Instruction Features
(16 bits). Data is transferred from the top word of the source register. Data is transferred to the top
word of the destination register and the bottom word is automatically cleared with zeros.
Specifying a conditional instruction as the operation instruction executed in parallel has no effect
on the data transfer instructions.
X and Y memory data transfers access only the X and Y memory; they cannot access other
memory areas.
4.16.2
Single data transfers execute only one data transfer. They use 16-bit instruction code. Single data
transfers cannot be processed in parallel with ALU operations. The X pointer, which accesses X
memory, and two added pointers are valid; the Y pointer is not valid. As with the SuperH RISC
engine, single data transfers can access all memory areas, including external memory. Except for
the DSR register, the DSP registers can be specified as source and destination operands. (The DSR
register is defined as the system register, so it can transfer data with LDS and STS instructions.)
Rev. 5.00 Jun 30, 2004 page 78 of 512
REJ09B0171-0500O
Single Data Transfers
X pointer (R4, R5)
Figure 4.19 Flowchart of X and Y Memory Data Transfers
(RAM, ROM)
X memory
X0
X1
A0
A1
XDB[15:0]
XAB[15:1]
: Not affected for storing; cleared for loading
: Cannot be set
0, +2, +R8
Y0
Y1
M0
M1
A0G
Y pointer (R6, R7)
A1G DSR
(RAM, ROM)
Y memory
YDB[15:0]
YAB[15:1]
0, +2, +R9