MC9S12HZ256CAL Freescale Semiconductor, MC9S12HZ256CAL Datasheet - Page 135
MC9S12HZ256CAL
Manufacturer Part Number
MC9S12HZ256CAL
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12HZ128CAL.pdf
(692 pages)
Specifications of MC9S12HZ256CAL
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4.3.3.3
Read: Anytime. Write: Anytime.
This register configures port pins PM[5:2] as either input or output.
When a CAN module is enabled, the corresponding transmitter (TXCANx) pin becomes an output, the
corresponding receiver (RXCANx) pin becomes an input, and the associated Data Direction Register bits
have no effect. If a CAN module is disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
4.3.3.4
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Freescale Semiconductor
DDRM[5:2]
RDRM[5:2]
Reset
Reset
Field
Field
5:2
5:2
W
W
R
R
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Reduced Drive Port M
0 Full drive strength at output
1 Associated pin drives at about 1/3 of the full drive strength.
Port M Data Direction Register (DDRM)
Port M Reduced Drive Register (RDRM)
0
0
0
0
7
7
= Reserved or Unimplemented
= Reserved or Unimplemented
0
0
0
0
6
6
Figure 4-19. Port M Reduced Drive Register (RDRM)
Figure 4-18. Port M Data Direction Register (DDRM)
Table 4-13. DDRM Field Descriptions
Table 4-14. RDRM Field Descriptions
DDRM5
RDRM5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
5
DDRM4
RDRM4
0
0
4
4
Description
Description
DDRM3
RDRM3
0
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRM2
RDRM2
0
0
2
2
0
0
0
0
1
1
0
0
0
0
0
0
135
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