MC9S12HZ256CAL Freescale Semiconductor, MC9S12HZ256CAL Datasheet - Page 101
MC9S12HZ256CAL
Manufacturer Part Number
MC9S12HZ256CAL
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12HZ128CAL.pdf
(692 pages)
Specifications of MC9S12HZ256CAL
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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All bits read 0 and are not writable.
3.3.2.4
The ECNFG register enables the EEPROM interrupts.
CBEIE and CCIE bits are readable and writable while bits 5-0 read 0 and are not writable.
3.3.2.5
The EPROT register defines which EEPROM sectors are protected against program or erase.
The EPROT register is loaded from EEPROM array address 0x07FD during reset, as indicated by the F in
Figure
All bits in the EPROT register are readable. Bits NV[6:4] are not writable. The EPOPEN and EPDIS bits
in the EPROT register can only be written to the protected state (i.e., 0). The EP[2:0] bits can be written
anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, then the state of the EPDIS and EP[2:0]
bits is irrelevant.
Freescale Semiconductor
Reset
CBEIE
Reset
Field
CCIE
7
6
W
W
R
R
3-8.
EPOPEN
CBEIE
Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty
command buffer in the EEPROM.
0 Command buffer empty interrupts disabled.
1 An interrupt will be requested whenever the CBEIF flag is set (see
Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being
completed in the EEPROM.
0 Command complete interrupts disabled.
1 An interrupt will be requested whenever the CCIF flag is set (see
EEPROM Configuration Register (ECNFG)
EEPROM Protection Register (EPROT)
F
7
0
7
(ESTAT)”).
(ESTAT)”).
= Unimplemented or Reserved
= Unimplemented or Reserved
CCIE
NV6
6
0
6
F
Figure 3-7. EEPROM Configuration Register (ECNFG)
Figure 3-8. EEPROM Protection Register (EPROT)
Table 3-4. ECNFG Field Descriptions
MC9S12HZ256 Data Sheet, Rev. 2.05
NV5
5
0
0
5
F
NV4
4
0
0
4
F
Description
EPDIS
F
3
0
0
3
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
Section 3.3.2.6, “EEPROM Status Register
Section 3.3.2.6, “EEPROM Status Register
EP2
2
0
0
2
F
EP1
1
0
0
1
F
EP0
F
0
0
0
0
101
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