DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 123
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.2.28 (2)
DIVXU (DIVide eXtend as Unsigned)
Operation
ERd
Assembly-Language Format
DIVXU.W Rs, ERd
Operand Size
Word
Description
This instruction divides the contents of a 32-bit register ERd (destination operand) by the contents
of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The
division is unsigned. The operation performed is 32 bits
remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The
remainder is placed in the upper 16 bits of (Ed).
Valid results are not assured if division by zero is attempted or an overflow occurs.
Available Registers
ERd: ER0 to ER7
Rs:
R0 to R7, E0 to E7
Rs
DIVXU (W)
ERd
Dividend
32 bits
ERd
Divisor
16 bits
Rs
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the divisor is negative;
Z: Set to 1 if the divisor is zero; otherwise
V: Previous value remains unchanged.
C: Previous value remains unchanged.
otherwise cleared to 0.
cleared to 0.
Remainder
Rev. 4.00 Feb 24, 2006 page 107 of 322
—
I
16 bits
16 bits
UI H
—
Section 2 Instruction Descriptions
ERd
—
16-bit quotient and 16-bit
Quotient
16 bits
—
U
N
REJ09B0139-0400
Z
— —
V
C
Divide
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