DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 116
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 2 Instruction Descriptions
2.2.26 (3)
DEC (DECrement)
Operation
ERd – 1
ERd – 2
Assembly-Language Format
DEC.L #1, ERd
DEC.L #2, ERd
Operand Size
Longword
Description
This instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register ERd
(destination operand) and stores the result in the 32-bit register ERd.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
An overflow is caused by the operations H'80000000 – 1
H'7FFFFFFE, and H'80000001 – 2
Rev. 4.00 Feb 24, 2006 page 100 of 322
REJ09B0139-0400
Register direct
Register direct
Addressing
Mode
ERd
ERd
DEC (L)
Mnemonic
DEC.L
DEC.L
Operands
#1, ERd
#2, ERd
H'7FFFFFFF.
1st byte
1
1
B
B
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Previous value remains unchanged.
2nd byte
7
F
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
—
I
0 erd
0 erd
H'7FFFFFFF, H'80000000 – 2
UI H
—
—
3rd byte
—
U
N
4th byte
Z
V
Decrement
—
States
No. of
C
1
1
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