M38507F8AFP#U1 Renesas Electronics America, M38507F8AFP#U1 Datasheet - Page 22

• Manufacturer Part Number: M38507F8AFP#U1
• Description: IC 740/3850 MCU FLASH 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38507F8AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 12.5 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
Table 8
NOTES:
Reset
INT
Reserved
INT
INT
INT
Reserved
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O1 reception
Serial I/O1
Transmission
CNTR
CNTR
A/D converter
BRK instruction
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Interrupt Source
0
1
2
3
/Serial I/O2
(2)
0
1
Interrupt vector addresses and priority
Apr 17, 2009
Priority
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
Page 20 of 56
FFED
FFDD
FFFD
FFFB
FFEF
FFEB
FFE7
FFDF
FFF9
FFF7
FFF5
FFF3
FFF1
FFE9
FFE5
FFE3
FFE1
High
Addresses
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Vector
16
16
FFEC
FFDE
FFDC
FFFC
FFFA
FFEE
FFEA
FFE8
FFE6
FFE4
FFE2
FFE0
FFF8
FFF6
FFF4
FFF2
FFF0
Low
(1)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At reset
At detection of either rising or falling
edge of INT
Reserved
At detection of either rising or falling
edge of INT
At detection of either rising or falling
edge of INT
At detection of either rising or falling
edge of INT
serial I/O2 data reception/transmission
Reserved
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O1 data
reception
At completion of serial I/O1 transfer
shift or when transmission buffer is
empty
At detection of either rising or falling
edge of CNTR
At detection of either rising or falling
edge of CNTR
At completion of A/D conversion
At BRK instruction execution
Interrupt Request Generating
0
1
2
3
input
input
input
input/ At completion of
Conditions
0
1
input
input
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Switch by Serial I/O2/INT
source bit
STP release timer underflow
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
Remarks
3
interrupt