C8051F902-GU Silicon Laboratories Inc, C8051F902-GU Datasheet - Page 246
![IC MCU 8BIT 8KB FLASH 24QSOP](/photos/12/15/121586/c8051f9xx_24-qsop_sml.jpg)
C8051F902-GU
Manufacturer Part Number
C8051F902-GU
Description
IC MCU 8BIT 8KB FLASH 24QSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F902-GU
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-QSOP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 15x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
768 B
Interface Type
UART
Maximum Clock Frequency
25 MHz
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F912DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Package
24QSOP
Device Core
8051
Family Name
C8051F90x
Maximum Speed
25 MHz
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1849-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F902-GU
Manufacturer:
SEMIKRON
Quantity:
45
Company:
Part Number:
C8051F902-GU
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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C8051F91x-C8051F90x
Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
246
0100
0101 0 X X
0010
0001
0000 0
0010 0
0001 0
0000 0
Values Read
0
0
0
0
0
0
0
0
0
1 X
0 X
1 X
0 X
1 X
0 X A slave byte was received.
1 X
1 X
1 X
0
1
Current SMbus State
A slave byte was transmitted;
NACK received.
A slave byte was transmitted;
ACK received.
A Slave byte was transmitted;
error detected.
An illegal STOP or bus error
was detected while a Slave
Transmission was in progress.
A slave address + R/W was
received; ACK sent.
Lost arbitration as master;
slave address + R/W received;
ACK sent.
A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
Lost arbitration while attempt-
ing a STOP.
Lost arbitration while attempt-
ing a repeated START.
Lost arbitration due to a
detected STOP.
Lost arbitration while transmit-
ting a data byte as master.
(Continued)
Rev. 1.0
Typical Response Options
No action required (expecting
STOP condition).
Load SMB0DAT with next data
byte to transmit.
No action required (expecting
Master to end transfer).
Clear STO.
If Write, Set ACK for first data
byte.
If Read, Load SMB0DAT with
data byte
If Write, Set ACK for first data
byte.
If Read, Load SMB0DAT with
data byte
Reschedule failed transfer
Clear STO.
No action required (transfer
complete/aborted).
Set ACK for next data byte;
Read SMB0DAT.
Set NACK for next data byte;
Read SMB0DAT.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Values to
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
Write
0 X 0001
0 X 0100
0 X 0001
0 X
0 1
0 X 0100
0 1
0 X 0100
0 X
0 X
0 0
0 1
0 0
0 X
0 X
0 X
0 X
0 X
0 X
0000
0000
0000
0000
1110
1110
1110
1110
-
-
-
-
-
-
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