C8051T606-GM Silicon Laboratories Inc, C8051T606-GM Datasheet - Page 7

• Manufacturer Part Number: C8051T606-GM
• Description: IC 8051 MCU 1.5K-EEPROM 11-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T60xr

Specifications of C8051T606-GM

• Program Memory Type: OTP
• Program Memory Size: 1.5KB (1.5K x 8)
• Package / Case: 11-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 6
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T606DK
• Minimum Operating Temperature: - 40 C
• Package: 11QFN EP
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1668 - CARD DAUGHTER QFN10 SOCKET336-1667 - CARD DAUGHTER MSOP SOCKET336-1666 - KIT DEVELOPMENT FOR C8051T606336-1404 - KIT DEV FOR C8051T60X MCU'S
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1662-5

13. Comparator0
14. CIP-51 Microcontroller
15. Memory Organization
16. Special Function Registers
17. Interrupts
18. Power Management Modes
19. Reset Sources
20. EPROM Memory
21. Oscillators and Clock Selection
22. Port Input/Output
23. SMBus
24. UART0
25. Timers
Figure 13.1. Comparator0 Functional Block Diagram ............................................. 59
Figure 13.2. Comparator Hysteresis Plot ................................................................ 60
Figure 13.3. Comparator Input Multiplexer Block Diagram ...................................... 63
Figure 14.1. CIP-51 Block Diagram ......................................................................... 65
Figure 15.1. Program Memory Map ......................................................................... 74
Figure 15.2. RAM Memory Map .............................................................................. 75
Figure 19.1. Reset Sources ..................................................................................... 92
Figure 19.2. Power-On and VDD Monitor Reset Timing ......................................... 93
Figure 21.1. Oscillator Options .............................................................................. 100
Figure 22.1. Port I/O Functional Block Diagram .................................................... 106
Figure 22.2. Port I/O Cell Block Diagram .............................................................. 107
Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 111
Figure 22.4. Priority Crossbar Decoder Example 1 - No Skipped Pins ................. 112
Figure 22.5. Priority Crossbar Decoder Example 2 - Skipping Pins ...................... 113
Figure 23.1. SMBus Block Diagram ...................................................................... 120
Figure 23.2. Typical SMBus Configuration ............................................................ 121
Figure 23.3. SMBus Transaction ........................................................................... 122
Figure 23.4. Typical SMBus SCL Generation ........................................................ 124
Figure 23.5. Typical Master Write Sequence ........................................................ 131
Figure 23.6. Typical Master Read Sequence ........................................................ 132
Figure 23.7. Typical Slave Write Sequence .......................................................... 133
Figure 23.8. Typical Slave Read Sequence .......................................................... 134
Figure 24.1. UART0 Block Diagram ...................................................................... 137
Figure 24.2. UART0 Baud Rate Logic ................................................................... 138
Figure 24.3. UART Interconnect Diagram ............................................................. 139
Figure 24.4. 8-Bit UART Timing Diagram .............................................................. 139
Figure 24.5. 9-Bit UART Timing Diagram .............................................................. 140
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 141
Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 148
Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 149
Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 150
Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 155
Rev. 1.2
C8051T600/1/2/3/4/5/6
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