C8051T606-GM Silicon Laboratories Inc, C8051T606-GM Datasheet - Page 67

• Manufacturer Part Number: C8051T606-GM
• Description: IC 8051 MCU 1.5K-EEPROM 11-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T60xr

Specifications of C8051T606-GM

• Program Memory Type: OTP
• Program Memory Size: 1.5KB (1.5K x 8)
• Package / Case: 11-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 6
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T606DK
• Minimum Operating Temperature: - 40 C
• Package: 11QFN EP
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1668 - CARD DAUGHTER QFN10 SOCKET336-1667 - CARD DAUGHTER MSOP SOCKET336-1666 - KIT DEVELOPMENT FOR C8051T606336-1404 - KIT DEV FOR C8051T60X MCU'S
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1662-5

Mnemonic
Arithmetic Operations
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Logical Operations
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
Table 14.1. CIP-51 Instruction Set Summary
Description
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Rev. 1.2
C8051T600/1/2/3/4/5/6
Bytes
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
Cycles
Clock
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
1
2
2
2
2
3
1
2
2
3
1
2
2
2
2
67