EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 42

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

EP9315
Enhanced Universal Platform SOC Processor
42
HSTROBE
HSTROBE
DDMARDYn
DD (15:0)
DD (15:0)
HSTROBE
(device)
(device)
DD (15:0)
DMACKn
DMARQ
(device)
(device)
(host)
(host)
Note:
Note:
STOP
(host)
(host)
(host)
(host)
DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are
driven by the host.
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t
2. If the t
negated.
t
DH
t
DVH
SR
timing is not satisfied, the device may receive zero, one, or two more data words from the host.

Figure 28. Device Pausing an Ultra DMA data-out Burst
t
Copyright 2010 Cirrus Logic (All Rights Reserved)
CYCWR
Figure 27. Sustained Ultra DMA data-out Burst
t
DS
t
SR
t
DVS
t
2CYCWR
t
DH
t
DVH
t
CYCWR
t
RFS
t
DS
t
RP
t
DVS
t
t
DH
2CYCWR
t
DVH
RP
after DDMARDYn is
DS638F2