EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 15

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

Memory Interface
Figure 2
values for the timings of each of the SDRAM modes.
SDRAM Load Mode Register Cycle
DS638F2
SDCLK high time
SDCLK low time
SDCLK rise/fall time
Signal delay from SDCLK rising edge time
Signal hold from SDCLK rising edge time
DQMn delay from SDCLK rising edge time
DQMn hold from SDCLK rising edge time
DA valid setup to SDCLK rising edge time
DA valid hold from SDCLK rising edge time
SDWEn
SDCLK
SDCSn
DQMn
RASn
CASn
AD
DA
through
Figure 5
t
clkrf
define the timings associated with all phases of the SDRAM. The following table contains the
Parameter
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

t
d
Copyright 2010 Cirrus Logic (All Rights Reserved)
OP-Code
t
h
Symbol
t
t
clk_high
clk_low
t
t
t
t
t
DQd
DQh
DAh
clkrf
DAs
t
t
d
h
Enhanced Universal Platform SOC Processor
t
Min
clk_low
1
1
2
3
-
-
-
-
-
(t
(t
HCLK
HCLK
Typ
t
2
-
-
-
-
-
-
clk_high
) / 2
) / 2
Max
4
8
8
-
-
-
-
-
-
EP9315
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
15