EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 14

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Memory Interface
Figure 2
values for the timings of each of the SDRAM modes.
SDRAM Load Mode Register Cycle
14
SDCLK high time
SDCLK low time
SDCLK rise/fall time
Signal delay from SDCLK rising edge time
Signal hold from SDCLK rising edge time
DQMn delay from SDCLK rising edge time
DQMn hold from SDCLK rising edge time
DA valid setup to SDCLK rising edge time
DA valid hold from SDCLK rising edge time
SDWEn
SDCLK
SDCSn
DQMn
RASn
CASn
AD
DA
through
Figure 5
t
clkrf
define the timings associated with all phases of the SDRAM. The following table contains the
Parameter
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

t
d
Copyright 2010 Cirrus Logic (All Rights Reserved)
OP-Code
t
h
Symbol
t
t
clk_high
clk_low
t
t
t
t
t
DQd
DQh
clkrf
DAs
DAh
t
t
d
h
Min
t
clk_low
1
1
2
3
-
-
-
-
-
(t
(t
HCLK
HCLK
Typ
2
-
-
-
-
-
-
t
clk_high
) / 2
) / 2
Max
4
8
8
-
-
-
-
-
-
DS653F2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns