LPC2158FBD100,551 NXP Semiconductors, LPC2158FBD100,551 Datasheet - Page 19

• Manufacturer Part Number: LPC2158FBD100,551
• Description: IC ARM7 MCU FLASH 512K 100LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2158FBD100,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 14x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC21
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 40 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, LCD-DEMO-LPC2158
• Development Tools By Supplier: OM11020
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4691; 935287349551; LPC2158FBD100-S

NXP Semiconductors
LPC2157_2158_1
Product data sheet
6.10.1 Features
6.11.1 Features
6.11 UARTs
The LPC2158 is equipped with a USB device controller that enables 12 Mbit/s data
exchange with a USB host controller. It consists of a register interface, serial interface
engine, endpoint buffer memory and DMA controller. The serial interface engine decodes
the USB data stream and writes data to the appropriate end point buffer memory. The
status of a completed USB transfer or error condition is indicated via status registers. An
interrupt is also generated if enabled.
A DMA controller can transfer data between an endpoint buffer and the USB RAM.
The LPC2157/2158 each contain two UARTs. In addition to standard transmit and receive
data lines, the UART1 also provides a full modem control handshake interface.
Compared to previous LPC2000 microcontrollers, UARTs in LPC2157/2158 introduce a
fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve
standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In
addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.
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Fully compliant with USB 2.0 Full-speed specification.
Supports 32 physical (16 logical) endpoints.
Supports control, bulk, interrupt and isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
RAM message buffer size based on endpoint realization and maximum packet size.
Supports SoftConnect and GoodLink LED indicator. These two functions are sharing
one pin.
Supports bus-powered capability with low suspend current.
Supports DMA transfer on all non-control endpoints.
One duplex DMA channel serves all endpoints.
Allows dynamic switching between CPU controlled and DMA modes.
Double buffer implementation for bulk and isochronous endpoints.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B and 14 B
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
LPC2158 UART1 equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
Rev. 01 — 15 October 2008
Single-chip 16-bit/32-bit microcontrollers
LPC2157/2158
© NXP B.V. 2008. All rights reserved.
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