LPC2158FBD100,551 NXP Semiconductors, LPC2158FBD100,551 Datasheet - Page 14
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LPC2158FBD100,551
Manufacturer Part Number
LPC2158FBD100,551
Description
IC ARM7 MCU FLASH 512K 100LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2157FBD100551.pdf
(45 pages)
Specifications of LPC2158FBD100,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 14x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
40 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
38
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, LCD-DEMO-LPC2158
Development Tools By Supplier
OM11020
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4691
935287349551
LPC2158FBD100-S
935287349551
LPC2158FBD100-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2158FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 3.
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LPC2157_2158_1
Product data sheet
Symbol
V
V
V
V
VREF
VBAT
SDA_LCD
SCL_LCD
SYNC
CLK
BP0 to BP3
S0 to S31
DD
DDA
DD(LCD)
LCD
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
Open-drain 5 V tolerant digital I/O I
functionality.
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured
for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital
section of the pad is disabled.
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When
configured as the DAC output, digital section of the pad is disabled.
5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value typically ranges from 60 k to 300 k .
Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision 2.0 (Full-speed and Low-speed mode only).
5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
Pad provides special analog functionality.
Pin description LPC2158
Pin
11, 27, 33 I
96
38
41
89
31
34
35
36
37
42 to 45
46 to 77
Type
I
I
I
I
I
I/O
I
I/O
I/O
O
O
2
C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
…continued
Description
3.3 V power supply: This is the power supply voltage for the core and I/O
ports.
Analog 3.3 V power supply: This should be nominally the same voltage as
V
used to power the on-chip ADC(s) and DAC.
1.8 V to 5.5 V power supply: Power supply voltage for the PCF8576D.
LCD power supply: LCD voltage.
ADC reference voltage: This should be nominally less than or equal to the
V
pin is used as a reference for ADC(s) and DAC.
RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC.
SDA LCD — I
SCL LCD — I
SYNC — cascade synchronization input/output
CLK — external clock input/output
BP0 to BP3: LCD backplane outputs.
S0 to S31: LCD segment outputs.
DD
DD
Rev. 01 — 15 October 2008
but should be isolated to minimize noise and error. This voltage is only
voltage but should be isolated to minimize noise and error. Level on this
2
2
C-bus clock signal for the LCD controller.
C-bus data signal for the LCD controller.
Single-chip 16-bit/32-bit microcontrollers
LPC2157/2158
© NXP B.V. 2008. All rights reserved.
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