ATMEGA325P-20AU Atmel, ATMEGA325P-20AU Datasheet - Page 164

• Manufacturer Part Number: ATMEGA325P-20AU
• Description: IC MCU AVR 32K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325P-20AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1 KB
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 5.5 V, 5.8 V
• Supply Voltage (min): 2.4 V, 2.7 V
• Width: 14 mm
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA325P-16AU; ATMEGA325P-16AU

18.2.1
164
ATmega325P/3250P
AVR USART vs. AVR UART – Compatibility
Figure 18-1. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers.
• Baud Rate Generation.
1. Refer to
75
for USART pin placement.
Figure 1-1 on page
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Transmit)
UDR (Receive)
UBRR[H:L]
2,
(1)
Figure 1-2 on page
UCSRB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
OSC
DATA
3,
”Alternate Functions of Port E” on page
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
UCSRC
XCK
8023F–AVR–07/09
TxD
RxD