DSPIC30F2011-20I/ML Microchip Technology, DSPIC30F2011-20I/ML Datasheet - Page 22
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DSPIC30F2011-20I/ML
Manufacturer Part Number
DSPIC30F2011-20I/ML
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2011-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DAF30-4 - DEVICE ATP FOR ICE4000
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201120IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2011-20I/ML
Manufacturer:
Microchip Technology
Quantity:
135
clocked out. The programmer can begin to clock out
the response 20 μsec after PGD is brought low, and it
must provide the necessary amount of clock pulses to
receive the entire response from the programming
executive.
Once the entire response is clocked out, the
programmer should terminate the clock on PGC until it
is time to send another command to the programming
executive. This protocol is illustrated in
7.3
In Enhanced ICSP mode, the dsPIC30F operates from
the fast internal RC oscillator, which has a nominal
frequency of 7.37 MHz. This oscillator frequency yields
an effective system clock frequency of 1.84 MHz. Since
the SPI module operates in Slave mode, the
programmer must limit the SPI clock rate to a
frequency no greater than 1 MHz.
FIGURE 7-2:
DS70102K-page 22
Note:
PGC
PGD
SPI Rate
If the programmer provides the SPI with a
clock faster than 1 MHz, the behavior of
the
unpredictable.
programming
1
MSB X X X LSB
Last Command Word
PGC = Input
PGD = Input
2
Host Transmits
PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
15 16
executive
P8
Figure
PGC = Input (Idle)
PGD = Output
will
7-2.
Programming Executive
Processes Command
P9a
1
be
P9b
0
7.4
The programming executive uses no Watchdog Timer
or time out for transmitting responses to the
programmer. If the programmer does not follow the flow
control mechanism using PGC, as described in
Section 7.2 “Communication Interface and Proto-
col”, it is possible that the programming executive will
behave unexpectedly while trying to send a response
to the programmer. Since the programming executive
has no time out, it is imperative that the programmer
correctly follow the described communication protocol.
As a safety measure, the programmer should use the
command time outs identified in
command time out expires, the programmer should
reset
programming the device again.
P10
the
Time Outs
1
MSB X X X LSB
2
programming
Host Clocks Out Response
15 16
PGC = Input
PGD = Output
© 2010 Microchip Technology Inc.
P11
1
executive
MSB X X X LSB
2
Table
15 16
8-1. If the
and
start