DSPIC30F2011-20I/ML Microchip Technology, DSPIC30F2011-20I/ML Datasheet - Page 2
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DSPIC30F2011-20I/ML
Manufacturer Part Number
DSPIC30F2011-20I/ML
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2011-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DAF30-4 - DEVICE ATP FOR ICE4000
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201120IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2011-20I/ML
Manufacturer:
Microchip Technology
Quantity:
135
2.2
The pins identified in
programming. Refer to the appropriate device data
sheet for complete pin descriptions.
TABLE 2-1:
2.3
The program memory space extends from 0x0 to
0xFFFFFE. Code storage is located at the base of the
memory map and supports up to 144 Kbytes (48K
instruction words). Code is stored in three, 48 Kbyte
memory panels that reside on-chip.
the location and program memory size of each device.
TABLE 2-2:
DS70102K-page 2
MCLR/V
V
V
PGC
PGD
Legend: I = Input, O = Output, P = Power
dsPIC30F2010
dsPIC30F2011
dsPIC30F2012
dsPIC30F3010
dsPIC30F3011
dsPIC30F3012
dsPIC30F3013
dsPIC30F3014
dsPIC30F4011
dsPIC30F4012
dsPIC30F4013
dsPIC30F5011
dsPIC30F5013
dsPIC30F5015
dsPIC30F5016
dsPIC30F6010
dsPIC30F6010A
dsPIC30F6011
dsPIC30F6011A
dsPIC30F6012
dsPIC30F6012A
dsPIC30F6013
dsPIC30F6013A
dsPIC30F6014
dsPIC30F6014A
dsPIC30F6015
DD
SS
Pin Name
Pins Used During Programming
Program Memory Map
Device
PP
Pin Type
dsPIC30F PIN DESCRIPTIONS
DURING PROGRAMMING
CODE MEMORY AND DATA EEPROM MAP AND SIZE
I/O
P
P
P
I
Table 2-1
Programming Enable
Power Supply
Ground
Serial Clock
Serial Data
Pin Description
are used for device
(Size in Instruction Words)
0x000000-0x007FFE (16K)
0x000000-0x007FFE (16K)
0x000000-0x007FFE (16K)
0x000000-0x00AFFE (22K)
0x000000-0x00AFFE (22K)
0x000000-0x00AFFE (22K)
0x000000-0x00AFFE (22K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
0x000000-0x015FFE (44K)
0x000000-0x015FFE (44K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
0x000000-0x015FFE (44K)
0x000000-0x015FFE (44K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
0x000000-0x001FFE (4K)
0x000000-0x001FFE (4K)
0x000000-0x001FFE (4K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
Table 2-2
Code Memory map
shows
Locations 0x800000 through 0x8005BE are reserved
for executive code memory. This region stores either
the programming executive or debugging executive.
The programming executive is used for device
programming, while the debug executive is used for in-
circuit debugging. This region of memory cannot be
used to store user code.
Locations 0xF80000 through 0xF8000E are reserved
for the Configuration registers. The bits in these
registers may be set to select various device options,
and are described in
Programming”.
Locations 0xFF0000 and 0xFF0002 are reserved for
the Device ID registers. These bits can be used by the
programmer to identify what device type is being
programmed and are described in
“Device
after code protection is applied.
Figure 2-2
dsPIC30F devices.
2.4
The Data EEPROM array supports up to 4 Kbytes of
data and is located in one memory panel. It is mapped
in program memory space, residing at the end of User
Memory Space (see
location and size of data EEPROM in each device.
Data EEPROM Memory
ID”. The device ID reads out normally, even
illustrates the memory map for the
Data EEPROM Memory Map
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FF000-0x7FFFFE (4K)
0x7FF800-0x7FFFFE (2K)
0x7FF800-0x7FFFFE (2K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFE (4K)
0x7FF800-0x7FFFFE (2K)
0x7FF800-0x7FFFFE (2K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFF (4K)
Section 5.7 “Configuration Bits
Figure
© 2010 Microchip Technology Inc.
(Size in Bytes)
None (0K)
None (0K)
2-2).
Table 2-2
Section 10.0
shows the