ATMEGA168V-10AU Atmel, ATMEGA168V-10AU Datasheet - Page 130
![IC AVR MCU 16K 10MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA168V-10AU
Manufacturer Part Number
ATMEGA168V-10AU
Description
IC AVR MCU 16K 10MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATAVRTS2080B.pdf
(378 pages)
2.ATMEGA48-20AU.pdf
(35 pages)
3.ATMEGA168V-10AU.pdf
(377 pages)
Specifications of ATMEGA168V-10AU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
23
Number Of Timers
3 bit
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
10MHz
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA168V-10AU
Manufacturer:
Atmel
Quantity:
41 576
Part Number:
ATMEGA168V-10AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 130 of 377
- Download datasheet (9Mb)
16.11 Register description
16.11.1
2545T–AVR–05/11
TCCR1A – Timer/Counter1 control register A
• Bit 7:6 – COM1A1:0: Compare output mode for channel A
• Bit 5:4 – COM1B1:0: Compare output mode for channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting.
WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 16-1.
Table 16-2
PWM mode.
Table 16-2.
Bit
(0x80)
Read/write
Initial value
COM1A1/COM1B1
COM1A1/COM1B1
0
0
1
1
0
0
1
1
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast
COM1A1
Compare output mode, non-PWM.
Compare output mode, fast PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
COM1A0/COM1B0
R/W
6
0
0
1
0
1
0
1
0
1
COM1B1
R/W
Table 16-1
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OC1A/OC1B disconnected
Toggle OC1A/OC1B on compare match
Clear OC1A/OC1B on compare match
(set output to low level)
Set OC1A/OC1B on compare match
(set output to high level)
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 14 or 15: Toggle OC1A on compare
match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OC1A/OC1B on compare match,
set OC1A/OC1B at BOTTOM (non-inverting mode)
Set OC1A/OC1B on compare match,
clear OC1A/OC1B at BOTTOM (invertiong mode)
shows the COM1x1:0 bit functionality when the
(1)
.
R
3
0
–
ATmega48/88/168
R
2
0
–
WGM11
R/W
1
0
WGM10
R/W
0
0
TCCR1A
130
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