PIC18LF2321-I/SS Microchip Technology, PIC18LF2321-I/SS Datasheet - Page 384
![IC PIC MCU FLASH 4KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2321-I/SS
Manufacturer Part Number
PIC18LF2321-I/SS
Description
IC PIC MCU FLASH 4KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(402 pages)
3.PIC18F2221-ISO.pdf
(8 pages)
4.PIC18F2221-ISO.pdf
(30 pages)
5.PIC18F2221-ISO.pdf
(46 pages)
6.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18LF2321-I/SS
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2221-ISO PDF datasheet #5
- PIC18F2321-IML PDF datasheet #6
- Current page: 384 of 396
- Download datasheet (7Mb)
PIC18F4321 FAMILY
BSF .................................................................................. 285
BTFSC ............................................................................. 286
BTFSS .............................................................................. 286
BTG .................................................................................. 287
BZ ..................................................................................... 288
C
C Compilers
CALL ................................................................................ 288
CALLW ............................................................................. 317
Capture (CCP Module) ..................................................... 141
Capture (ECCP Module) .................................................. 148
Capture/Compare/PWM (CCP) ........................................ 139
Clock Sources .................................................................... 29
CLRF ................................................................................ 289
CLRWDT .......................................................................... 289
Code Examples
Code Protection ....................................................... 253, 268
DS39689E-page 382
MPLAB C18 ............................................................. 324
MPLAB C30 ............................................................. 324
Associated Registers ............................................... 143
CCP Pin Configuration ............................................. 141
CCPRxH:CCPRxL Registers ................................... 141
Prescaler .................................................................. 141
Software Interrupt .................................................... 141
Timer1/Timer3 Mode Selection ................................ 141
Capture Mode. See Capture.
CCPRxH Register .................................................... 140
CCPRxL Register ..................................................... 140
Compare Mode. See Compare.
Interaction of Two CCP Modules ............................. 140
Module Configuration ............................................... 140
Pin Assignment ........................................................ 140
Timer Resources ...................................................... 140
Selecting the 31 kHz Source ...................................... 30
Selection Using OSCCON Register ........................... 30
16 x 16 Signed Multiply Routine ................................ 90
16 x 16 Unsigned Multiply Routine ............................ 90
8 x 8 Signed Multiply Routine .................................... 89
8 x 8 Unsigned Multiply Routine ................................ 89
Address Masking ..................................................... 176
Changing Between Capture Prescalers ................... 141
Computed GOTO Using an Offset Value ................... 56
Data EEPROM Read ................................................. 85
Data EEPROM Refresh Routine ................................ 86
Data EEPROM Write ................................................. 85
Erasing a Flash Program Memory Row ..................... 78
Fast Register Stack .................................................... 56
How to Clear RAM (Bank 1) Using
Implementing a Real-Time Clock
Initializing PORTA .................................................... 105
Initializing PORTB .................................................... 108
Initializing PORTC .................................................... 111
Initializing PORTD .................................................... 114
Initializing PORTE .................................................... 117
Loading the SSPBUF (SSPSR) Register ................. 164
Reading a Flash Program Memory Word .................. 77
Saving STATUS, WREG and
Writing to Flash Program Memory ....................... 80–81
Associated Registers ............................................... 269
Configuration Register Protection ............................ 271
Data EEPROM ......................................................... 271
Program Memory ..................................................... 269
Indirect Addressing ............................................ 67
Using a Timer1 Interrupt Service ..................... 131
BSR Registers in RAM ..................................... 103
Preliminary
COMF .............................................................................. 290
Comparator ...................................................................... 237
Comparator Specifications ............................................... 343
Comparator Voltage Reference ....................................... 243
Compare (CCP Module) .................................................. 142
Compare (ECCP Module) ................................................ 148
Computed GOTO ............................................................... 56
Configuration Bits ............................................................ 253
Context Saving During Interrupts ..................................... 103
Conversion Considerations .............................................. 378
CPFSEQ .......................................................................... 290
CPFSGT .......................................................................... 291
CPFSLT ........................................................................... 291
Crystal Oscillator/Ceramic Resonator ................................ 23
Customer Change Notification Service ............................ 391
Customer Notification Service ......................................... 391
Customer Support ............................................................ 391
D
Data Addressing Modes .................................................... 67
Data EEPROM Memory ..................................................... 83
Analog Input Connection Considerations ................ 241
Associated Registers ............................................... 241
Configuration ........................................................... 238
Effects of a Reset .................................................... 240
Interrupts ................................................................. 240
Operation ................................................................. 239
Operation During Sleep ........................................... 240
Outputs .................................................................... 239
Reference ................................................................ 239
Response Time ........................................................ 239
Accuracy and Error .................................................. 244
Associated Registers ............................................... 245
Configuring .............................................................. 243
Connection Considerations ...................................... 244
Effects of a Reset .................................................... 244
Operation During Sleep ........................................... 244
Associated Registers ............................................... 143
CCPRx Register ...................................................... 142
Pin Configuration ..................................................... 142
Software Interrupt .................................................... 142
Special Event Trigger .............................. 137, 142, 236
Timer1/Timer3 Mode Selection ................................ 142
Special Event Trigger .............................................. 148
Comparing Options with the
Direct ......................................................................... 67
Indexed Literal Offset ................................................ 69
Indirect ....................................................................... 67
Inherent and Literal .................................................... 67
Associated Registers ................................................. 87
EEADR Register ........................................................ 83
EECON1 and EECON2 Registers ............................. 83
EEDATA Register ...................................................... 83
Operation During Code-Protect ................................. 86
Protection Against Spurious Write ............................. 86
Reading ..................................................................... 85
Using ......................................................................... 86
Write Verify ................................................................ 85
Writing ....................................................................... 85
External Signal ................................................ 239
Internal Signal .................................................. 239
Extended Instruction Set Enabled ..................... 70
Instructions Affected .......................................... 69
© 2007 Microchip Technology Inc.
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