PIC18LF2321-I/SS Microchip Technology, PIC18LF2321-I/SS Datasheet - Page 265
![IC PIC MCU FLASH 4KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2321-I/SS
Manufacturer Part Number
PIC18LF2321-I/SS
Description
IC PIC MCU FLASH 4KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(402 pages)
3.PIC18F2221-ISO.pdf
(8 pages)
4.PIC18F2221-ISO.pdf
(30 pages)
5.PIC18F2221-ISO.pdf
(46 pages)
6.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18LF2321-I/SS
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2221-ISO PDF datasheet #5
- PIC18F2321-IML PDF datasheet #6
- Current page: 265 of 396
- Download datasheet (7Mb)
23.2
For PIC18F4321 family devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
FIGURE 23-1:
© 2007 Microchip Technology Inc.
Change on IRCF bits
All Device Resets
INTRC Source
Watchdog Timer (WDT)
WDTPS<3:0>
SWDTEN
CLRWDT
WDTEN
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
÷128
4
Preliminary
Programmable Postscaler
1:1 to 1:32,768
23.2.1
Register 23-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
PIC18F4321 FAMILY
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
Reset
DS39689E-page 263
WDT
Reset
Wake-up from
Power-Managed
Modes
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