PIC18LF2321-I/SS Microchip Technology, PIC18LF2321-I/SS Datasheet - Page 238
![IC PIC MCU FLASH 4KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2321-I/SS
Manufacturer Part Number
PIC18LF2321-I/SS
Description
IC PIC MCU FLASH 4KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(402 pages)
3.PIC18F2221-ISO.pdf
(8 pages)
4.PIC18F2221-ISO.pdf
(30 pages)
5.PIC18F2221-ISO.pdf
(46 pages)
6.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18LF2321-I/SS
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2221-ISO PDF datasheet #5
- PIC18F2321-IML PDF datasheet #6
- Current page: 238 of 396
- Download datasheet (7Mb)
PIC18F4321 FAMILY
19.8
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
TABLE 19-2:
DS39689E-page 236
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(1)
2:
3:
(1)
Use of the CCP2 Trigger
These registers and/or bits are unimplemented on 28-pin devices and are read as ‘0’.
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
TRISA7
PSPIE
PSPIP
PSPIF
OSCFIF
OSCFIE
OSCFIP
RA7
ADFM
Bit 7
RB7
IBF
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(2)
(1)
(1)
(1)
(2)
bits
TRISA6
RA6
CMIF
CMIE
CMIP
ADIF
ADIE
ADIP
Bit 6
OBF
RB6
—
—
—
—
—
(CCP2CON<3:0>)
(2)
(2)
PORTA Data Direction Control Register
VCFG1
ACQT2
CHS3
RCIF
RCIE
RCIP
IBOV
Bit 5
RA5
RB5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
Preliminary
CHS2
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 4
TXIF
be
RA4
RB4
—
—
PCFG3
ACQT0
SSPIF
SSPIE
SSPIP
BCLIE
BCLIP
RE3
BCLIF
CHS1
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
RBIE
Bit 3
RA3
RB3
ACQ
—
—
(3)
time selected before the Special Event Trigger
PORTE Data Latch Register
TMR0IF
CCP1IE
CCP1IP
CCP1IF
HLVDIF
HLVDIE
HLVDIP
TRISE2
PCFG2
ADCS2
RE2
CHS0
Bit 2
RA2
RB2
(1)
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISE1
PCFG1
ADCS1
INT0IF
RE1
Bit 1
© 2007 Microchip Technology Inc.
RA1
RB1
(1)
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISE0
PCFG0
ADCS0
ADON
RE0
RBIF
Bit 0
RA0
RB0
(1)
on page
Values
Reset
49
52
52
52
52
52
52
51
51
52
52
52
52
52
52
52
52
51
51
51
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