PIC16F636-I/ST Microchip Technology, PIC16F636-I/ST Datasheet - Page 87

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PIC16F636-I/ST

Manufacturer Part Number
PIC16F636-I/ST
Description
IC MCU FLASH 2KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F636-I/ST

Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
14-TSSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LVD, POR, WDT
Number Of I /o
11
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
RS- 232/SPI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Package
14TSSOP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162057 - MPLAB ICD 2 HEADER 14DIP
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Quantity
Price
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0
PIC12F635/PIC16F636/639
11.15 Configurable Output Enable Filter
The purpose of this filter is to enable the LFDATA output
and wake the microcontroller only after receiving a
specific sequence of pulses on the LC input pins.
Therefore, it prevents the AFE from waking up the
microcontroller due to noise or unwanted input signals.
The circuit compares the timing of the demodulated
header waveform with a pre-defined value, and enables
the demodulated LFDATA output when a match occurs.
The output enable filter consists of a high (T
) and
OEH
low duration (T
) of a pulse immediately after the
OEL
AGC settling gap time. The selection of high and low
times further implies a max period time. The output
enable high and low times are determined by SPI
interface programming. Figure 11-5 and Figure 11-6
show the output enable filter waveforms.
There should be no missing cycles during T
.
OEH
Missing cycles may result in failing the output enable
condition.
FIGURE 11-5:
OUTPUT ENABLE FILTER TIMING
Required Output Enable Sequence
Data Packet
T
STAB
(T
+ T
)
AGC
PAGC
Demodulator
T
GAP
Output
t
T
t
T
OEH
OEL
Start bit
AGC
AFE
Wake-up
Gap Pulse
LFDATA output is enabled
and AGC Stabilization
t
T
OET
on this rising edge
Preliminary
© 2005 Microchip Technology Inc.
DS41232B-page 85

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