PIC12F629-I/MF Microchip Technology, PIC12F629-I/MF Datasheet - Page 48

• Manufacturer Part Number: PIC12F629-I/MF
• Description: IC MCU CMOS 8BIT 1K FLASH 8-DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F629-I/MF

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC12F629/675
7.3
The A/D converter module can operate during SLEEP.
This requires the A/D clock source to be set to the
internal RC oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from SLEEP.
If the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
TABLE 7-2:
DS41190E-page 46
05h
0Bh, 8Bh INTCON
0Ch
1Eh
1Fh
85h
8Ch
9Eh
9Fh
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.
Address
A/D Operation During SLEEP
GPIO
PIR1
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
ADCON0
TRISIO
PIE1
ADRESL
ANSEL
Name
SUMMARY OF A/D REGISTERS
Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
ADFM
EEIF
EEIE
Bit 7
GIE
—
—
—
ADCS2
VCFG
ADIE
Bit 6
PEIE
ADIF
—
—
TRISIO5
ADCS1
GPIO5
Bit 5
T0IE
—
—
—
TRISIO4
ADCS0
GPIO4
Bit 4
INTE
—
—
—
TRISIO3
GPIO3
CHS1
ANS3
CMIF
CMIE
GPIE
Bit 3
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.4
A device RESET forces all registers to their RESET
state. Thus the A/D module is turned off and any
pending conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
TRISIO2 TRISIO1 TRISIO0
GPIO2
CHS0
ANS2
Bit 2
T0IF
—
—
Effects of RESET
GPIO1
ANS1
Bit 1
INTF
GO
—
—
TMR1IF
TMR1IE
GPIO0
ADON
ANS0
© 2007 Microchip Technology Inc.
GPIF
Bit 0
--xx xxxx
0000 0000
00-- 0--0
xxxx xxxx
00-- 0000
--11 1111
00-- 0--0
xxxx xxxx
-000 1111
Value on:
POR,
BOD
--uu uuuu
0000 000u
00-- 0--0
uuuu uuuu
00-- 0000
--11 1111
00-- 0--0
uuuu uuuu
-000 1111
Value on
RESETS
all other