PIC12F629 Microchip Technology Inc., PIC12F629 Datasheet
PIC12F629
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PIC12F629 Summary of contents
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... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2007 Microchip Technology Inc. PIC12F629/675 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41190E ...
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... EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified logo, microID, MPLAB, PIC DSCs code hopping devices, Serial ® ® © 2007 Microchip Technology Inc. ® ...
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... PIC12F675 1024 * 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2007 Microchip Technology Inc. PIC12F629/675 Low Power Features: • Standby Current 2.0V, typical • Operating Current: - 8.5 μ kHz, 2.0V, typical - 100 μ ...
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... PIC12F629/675 Pin Diagrams 8-pin PDIP, SOIC, DFN-S GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/V GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/V DS41190E-page GP0/CIN+/ICSPDAT 2 7 GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/V REF 4 5 GP2/AN2/T0CKI/INT/COUT PP /ICSPCLK © 2007 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC12F629/675 DS41190E-page 3 ...
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... PIC12F629/675 NOTES: DS41190E-page 4 © 2007 Microchip Technology Inc. ...
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... Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC12F629 and PIC12F675 devices are covered by this Data Sheet. They are identical, except the PIC12F675 has a 10-bit A/D converter. They come in 8-pin PDIP, SOIC, and MLF-S packages. Figure 1-1 shows a block diagram of the PIC12F629/675 devices ...
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... PIC12F629/675 TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION Name Function GP0/AN0/CIN+/ICSPDAT GP0 AN0 CIN+ ICSPDAT GP1/AN1/CIN-/V / GP1 REF ICSPCLK AN1 CIN- V REF ICSPCLK GP2/AN2/T0CKI/INT/COUT GP2 AN2 T0CKI INT COUT GP3/MCLR/V GP3 PP MCLR V PP GP4/AN3/T1G/OSC2/ GP4 CLKOUT AN3 T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 T1CKI ...
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... MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F629/675 devices have a 13-bit program counter capable of addressing program memory space. Only the first (0000h - 03FFh) for the PIC12F629/675 devices is physically imple- mented. Accessing a location above these boundaries will cause a wrap around within the first space. ...
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... The Special Function registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS41190E-page 8 FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F629/675 File Address (1) Indirect addr. 00h Indirect addr. TMR0 ...
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... INTE GPIE T0IF — — CMIF — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — CINV CIS CM2 — — CHS1 CHS0 PIC12F629/675 Value on Bit 1 Bit 0 POR, BOD 18,59 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx GPIO1 GPIO0 --xx xxxx — — ...
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... PIC12F629/675 TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (1) 80h INDF Addressing this Location uses Contents of FSR to Address Data Memory 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter's (PC) Least Significant Byte 83h STATUS (2) IRP RP1 84h FSR ...
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... STATUS bits. For other instructions not affecting any STATUS bits, see the “Instruction Set Summary”. Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC12F629/675 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. ...
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... PIC12F629/675 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External GP2/INT interrupt • TMR0 • Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG — OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 GPPU INTEDG bit 7 bit 7 ...
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... T0IF bit. Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ...
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... PIC12F629/675 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ...
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... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User ...
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... PIC12F629/675 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON Register bits are shown in Register 2-6. REGISTER 2-6: PCON — POWER CONTROL REGISTER (ADDRESS: 8Eh) U-0 — ...
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... Microchip Technology Inc. PIC12F629/675 2.3.2 STACK The PIC12F629/675 family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed interrupt causes a branch ...
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... Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results operation (although STATUS bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F629/675 Direct Addressing (1) From Opcode RP1 RP0 6 ...
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... MOVLW 0Ch MOVWF TRISIO 3.2 Additional Pin Functions Every GPIO pin on the PIC12F629/675 has an interrupt-on-change option and every GPIO pin, except GP3, has a weak pull-up option. The next two sections describe these functions. 3.2.1 WEAK PULL-UP Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up ...
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... PIC12F629/675 REGISTER 3-2: TRISIO — GPIO TRI-STATE REGISTER (ADDRESS: 85h) U-0 — bit 7 bit 7-6: Unimplemented: Read as ’0’ bit 5-0: TRISIO<5:0>: General Purpose I/O Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated GPIO pin configured as an output. Note: TRISIO<3> always reads 1. Legend Readable bit ...
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... Q2 cycle), then the GPIF inter- rupt flag may not get set. U-0 R/W-0 R/W-0 R/W-0 — IOC5 IOC4 IOC3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared PIC12F629/675 R/W-0 R/W-0 R/W-0 IOC2 IOC1 IOC0 bit Bit is unknown DS41190E-page 21 ...
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... PIC12F629/675 3.3 Pin Descriptions and Diagrams Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. 3.3.1 GP0/AN0/CIN+ Figure 3-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: • ...
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... Master Clear Reset FIGURE 3-3: Data Bus RD TRISIO PORT Weak IOC RD IOC V DD Interrupt-on-Change I/O pin PIC12F629/675 PP BLOCK DIAGRAM OF GP3 MCLRE RESET I/O pin V SS MCLRE PORT DS41190E-page 23 ...
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... PIC12F629/675 3.3.5 GP4/AN3/T1G/OSC2/CLKOUT Figure 3-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D (PIC12F675 only) • a TMR1 gate input • a crystal/resonator connection • a clock output FIGURE 3-4: BLOCK DIAGRAM OF GP4 ...
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... IOC — — 9Fh ANSEL — ADCS2 Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by GPIO. © 2007 Microchip Technology Inc. PIC12F629/675 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GP5 GP4 GP3 GP2 GP1 T0IE INTE ...
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... PIC12F629/675 NOTES: DS41190E-page 26 © 2007 Microchip Technology Inc. ...
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... The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut-off during SLEEP 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA PIC12F629/675 edge (T0SE) control bit ® Reference Manual, Data Bus 8 SYNC 2 TMR0 Cycles Set Flag bit T0IF ...
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... PIC12F629/675 4.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... GPPU INTEDG 85h TRISIO — — Legend: — = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC12F629/675 EXAMPLE 4-1: bcf STATUS,RP0 clrwdt clrf TMR0 bsf STATUS,RP0 movlw b’00101111’ ;Required if desired ...
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... PIC12F629/675 5.0 TIMER1 MODULE WITH GATE CONTROL The PIC12F629/675 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • ...
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... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. PIC12F629/675 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...
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... PIC12F629/675 REGISTER 5-1: T1CON — TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 R/W-0 — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = Timer1 T1G pin is low 0 = Timer1 is on bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits ...
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... Bit 3 Bit 2 T0IE INTE GPIE T0IF — — CMIF — — — CMIE — PIC12F629/675 Value on Value on Bit 1 Bit 0 all other POR, BOD RESETS INTF GPIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — ...
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... PIC12F629/675 NOTES: DS41190E-page 34 © 2007 Microchip Technology Inc. ...
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... COMPARATOR MODULE The PIC12F629/675 devices have one analog comparator. The inputs to the comparator are multiplexed with the GP0 and GP1 pins. There is an on-chip Comparator Voltage Reference that can also REGISTER 6-1: CMCON — COMPARATOR CONTROL REGISTER (ADDRESS: 19h) U-0 — COUT bit 7 bit 7 Unimplemented: Read as ‘ ...
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... PIC12F629/675 6.1 Comparator Operation A single comparator is shown in Figure 6-1, along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
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... Multiplexed Input with Internal Reference and Output CM2:CM0 = 101 GP1/CIN- A COUT GP0/CIN+ A GP2/COUT D Multiplexed Input with Internal Reference CM2:CM0 = 110 GP1/CIN- A COUT GP0/CIN+ A GP2/COUT D PIC12F629/675 Off (Read as '0') COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF ...
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... PIC12F629/675 6.3 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 6-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V . The analog input, therefore, must be between SS V and the input voltage deviates from this ...
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... To minimize power consumption while in SLEEP mode, turn off the comparator, CM2:CM0 = 111, and voltage reference, VRCON<7> © 2007 Microchip Technology Inc. PIC12F629/675 The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range ...
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... PIC12F629/675 REGISTER 6-2: VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) R/W-0 VREN bit 7 bit 7 VREN: CV REF circuit powered on REF circuit powered down REF bit 6 Unimplemented: Read as '0' bit 5 VRR: CV Range Selection bit REF 1 = Low range 0 = High range bit 4 Unimplemented: Read as '0' ...
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... V is used. The VCFG bit (ADCON0<6>) REF © 2007 Microchip Technology Inc. PIC12F629/675 The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference ...
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... PIC12F629/675 TABLE 7-1: T vs. DEVICE OPERATING FREQUENCIES AD A/D Clock Source ( Operation ADCS2:ADCS0 2 T OSC 000 4 T OSC 100 8 T OSC 001 16 T OSC 101 32 T OSC 010 64 T OSC 110 A/D RC x11 Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical T 2: These values violate the minimum required T 3: For faster conversion times, the selection of another clock source is recommended ...
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... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Conversion STATUS bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. PIC12F629/675 U-0 U-0 R/W-0 R/W-0 — — CHS1 CHS0 W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC12F629/675 REGISTER 7-2: ANSEL — ANALOG SELECT REGISTER (ADDRESS: 9Fh) U-0 R/W-0 — ADCS2 bit 7 bit 7 Unimplemented: Read as ‘0’. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = F /2 OSC 001 = F /8 OSC 010 = F /32 OSC x11 = F (clock derived from a dedicated internal oscillator = 500 kHz max) ...
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... HOLD V DD Sampling Switch ≤ LEAKAGE V = 0.6V T ± 500 PIC12F629/675 the minimum acquisition time, , see ACQ SS C HOLD = DAC capacitance = 120 Sampling Switch (kΩ) DS41190E-page 45 ...
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... PIC12F629/675 7.3 A/D Operation During SLEEP The A/D converter module can operate during SLEEP. This requires the A/D clock source to be set to the internal RC oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion ...
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... EEDATA • EEADR EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC12F629/675 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. REGISTER 8-1: EEDAT — EEPROM DATA REGISTER (ADDRESS: 9Ah) ...
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... PIC12F629/675 8.1 EEADR The EEADR register can address maximum of 128 bytes of data EEPROM. Only seven of the eight bits in the register (EEADR<6:0>) are required. The MSb (bit 7) is ignored. The upper bit should always be ‘0’ to remain upward compatible with devices that have more data EEPROM memory ...
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... EEPROM. The WREN bit is not cleared by hardware. © 2007 Microchip Technology Inc. PIC12F629/675 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. ...
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... PIC12F629/675 8.7 DATA EEPROM OPERATION DURING CODE PROTECT Data memory can be code protected by programming the CPD bit to ‘0’. When the data memory is code protected, the CPU is able to read and write data to the Data EEPROM recommended to code protect the program memory when code protecting data memory ...
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... ID Locations • In-Circuit Serial Programming © 2007 Microchip Technology Inc. PIC12F629/675 The PIC12F629/675 has a Watchdog Timer that is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable ...
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... LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as specified in the PIC12F629/675 Programming Specification. These bits are reflected in an export of the configuration word. Microchip Development Tools maintain all calibration bits to factory settings ...
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... Oscillator Configurations 9.2.1 OSCILLATOR TYPES The PIC12F629/675 can be operated in eight different oscillator option modes. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC External Resistor/Capacitor (2 modes) • ...
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... EXAMPLE 9-1: bsf call movwf bcf 9.2.6 CLKOUT Internal Clock The PIC12F629/675 devices can be configured to provide a clock out signal in the INTOSC and RC oscillator modes. When configured, the oscillator frequency divided by four (F GP4/OSC2/CLKOUT pin. F purposes or to synchronize other logic. OSCILLATOR Z Section 12.0, for information /4 ...
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... RESET The PIC12F629/675 differentiates between various kinds of RESET: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during SLEEP d) MCLR Reset during normal operation e) MCLR Reset during SLEEP f) Brown-out Detect (BOD) Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a “ ...
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... PIC12F629/675 9.3.1 MCLR PIC12F629/675 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. ...
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... Then bringing MCLR high will begin execution immediately (see Figure 9-8). This is useful for testing purposes or to synchronize more than one PIC12F629/675 device operating in parallel. Table 9-6 shows the RESET conditions for some special registers, while Table 9-7 shows the RESET conditions for all the registers. © ...
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... PIC12F629/675 TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration PWRTE = 0 XT, HS PWRT 1024•T RC, EC, INTOSC T PWRT TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOD Legend unchanged unknown TABLE 9-5: ...
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... PIC12F629/675 • Wake-up from SLEEP through interrupt • Wake-up from SLEEP through WDT time-out uuuu uuuu — uuuu uuuu ( (4) uuuq quuu uuuu uuuu ...
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... PIC12F629/675 FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal RESET FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V ...
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... Interrupts The PIC12F629/675 has 7 sources of interrupt: • External Interrupt GP2/INT • TMR0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt (PIC12F675 only) • TMR1 Overflow Interrupt • EEPROM Data Write Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits ...
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... PIC12F629/675 FIGURE 9-10: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE ADIF (1) ADIE EEIF EEIE Note 1: PIC12F675 only. DS41190E-page 62 T0IF Wake-up (If in SLEEP mode) T0IE INTF INTE GPIF GPIE PEIE GIE © 2007 Microchip Technology Inc. ...
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... See Section 7.0 for operation of the A/D converter interrupt Interrupt Latency 2 PC+1 PC+1 Inst (PC+1) — Inst (PC) Dummy Cycle . Synchronous latency = where PIC12F629/675 by setting/clearing T0IE 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle = instruction cycle time. Latency CY DS41190E-page 63 ...
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... PIC12F629/675 TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS Address Name Bit 7 Bit 6 0Bh, 8Bh INTCON GIE PEIE 0Ch PIR1 EEIF ADIF 8Ch PIE1 EEIE ADIE Legend unknown unchanged unimplemented read as '0 value depends upon condition. Shaded cells are not used by the Interrupt module. 9.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack ...
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... Address Name Bit 7 Bit 6 81h OPTION_REG GPPU INTEDG 2007h Config. bits CP BODEN MCLRE PWRTE WDTE Legend Unchanged, shaded cells are not used by the Watchdog Timer. © 2007 Microchip Technology Inc. PIC12F629/675 1 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA Bit 5 Bit 4 ...
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... PIC12F629/675 9.7 Power-Down Mode (SLEEP) The Power-down mode is entered by executing a instruction. SLEEP If the Watchdog Timer is enabled: • WDT will be cleared but keeps running • PD bit in the STATUS register is cleared • TO bit is set • Oscillator driver is turned off • I/O ports maintain the status they had before ...
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... Program/Verify. Only the Least Significant 7 bits of the ID locations are used. 9.10 In-Circuit Serial Programming The PIC12F629/675 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for: • ...
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... PIC12F629/675 NOTES: DS41190E-page 68 © 2007 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC12F629/675 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC12F629/675 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction ...
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... PIC12F629/675 TABLE 10-2: PIC12F629/675 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. © 2007 Microchip Technology Inc. PIC12F629/675 BCF Bit Clear f Syntax: [label] BCF f,b 0 ≤ f ≤ 127 Operands: 0 ≤ b ≤ → ...
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... PIC12F629/675 CALL Call Subroutine Syntax: [ label ] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immedi- ate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH ...
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... Status Affected: Z Description: The contents of register 'f' are incremented the result is placed in the W register the result is placed back in register 'f'. © 2007 Microchip Technology Inc. PIC12F629/675 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: ( → ...
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... PIC12F629/675 MOVF Move f Syntax: [ label ] MOVF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (f) → (destination) Operation: Status Affected: Z Description: The contents of register f are moved to a destination dependant upon the status destination is W register the destination is file register f itself useful to test a file register, since status flag Z is affected ...
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... Carry Flag the result is placed in the W register the result is placed back in register 'f'. C Register f © 2007 Microchip Technology Inc. PIC12F629/675 SLEEP Syntax: [ label ] SLEEP Operands: None 00h → WDT, Operation: 0 → ...
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... PIC12F629/675 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register 'f' are exchanged the result is placed in the W register the result is placed in register 'f' ...
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... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC12F629/675 11.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... PIC12F629/675 11.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
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... Microchip Technology Inc. PIC12F629/675 11.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...
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... PIC12F629/675 11.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
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... DD - ∑ DIS the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. should be used when applying a "low" level to the MCLR pin, rather than Ω PIC12F629/675 + 0.3V ∑ {( ∑( DS41190E-page 81 ...
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... PIC12F629/675 FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. ...
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... FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. © 2007 Microchip Technology Inc. PIC12F629/675 Frequency (MHz) 20 DS41190E-page 83 ...
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... PIC12F629/675 12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001A D001B D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD DD internal Power-on Reset ...
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... DC Characteristics: PIC12F629/675-I (Industrial) Param Device Characteristics No. D010 Supply Current ( D011 D012 D013 D014 D015 D016 D017 † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all I from rail to rail ...
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... PIC12F629/675 12.3 DC Characteristics: PIC12F629/675-I (Industrial) Param Device Characteristics No. D020 Power-down Base Current ( D021 D022 D023 D024 D025 D026 † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base I peripheral is enabled. The peripheral Δ ...
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... DC Characteristics: PIC12F629/675-E (Extended) Param Device Characteristics No. D010E Supply Current ( D011E D012E D013E D014E D015E D016E D017E † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all I from rail to rail ...
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... PIC12F629/675 12.5 DC Characteristics: PIC12F629/675-E (Extended) Param Device Characteristics No. D020E Power-down Base Current ( D021E D022E D023E D024E D025E D026E † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base I peripheral is enabled. The peripheral Δ ...
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... DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) D033A OSC1 (HS mode) Input High Voltage V I/O ports IH D040 with TTL buffer ...
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... PIC12F629/675 12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.) DC CHARACTERISTICS Param Sym Characteristic No. Capacitive Loading Specs on Output Pins D100 C OSC2 pin OSC2 D101 C All I/O pins IO Data EEPROM Memory D120 E Byte Endurance D D120A E Byte Endurance D D121 V V for Read/Write DRW DD D122 T Erase/Write cycle time ...
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... for all pins for OSC2 output © 2007 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance Load Condition Pin V SS PIC12F629/675 DS41190E-page 91 ...
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... PIC12F629/675 12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED) FIGURE 12-5: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No. F External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period OSC (1) Oscillator Period Instruction Cycle Time 3 TosL, External CLKIN (OSC1) High ...
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... ST * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC12F629/675 Freq Min Typ† Max Units Tolerance ± ...
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... PIC12F629/675 FIGURE 12-6: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O pin (Input) I/O pin Old Value (Output) TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic No. 10 TosH2ckL OSC1↑ to CLK- OUT↓ 11 TosH2ckH OSC1↑ to CLK- OUT↑ 12 TckR CLKOUT rise time 13 TckF CLKOUT fall time ...
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... I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) RESET (due to BOD) Note delay only if PWRTE bit in configuration word is programmed to ‘0’. © 2007 Microchip Technology Inc. PIC12F629/675 (Device not in Brown-out Detect time-out 34 DS41190E-page 95 ...
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... PIC12F629/675 TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT DETECT REQUIREMENTS Param Sym Characteristic No MCLR Pulse Width (low Watchdog Timer Time-out WDT Period (No Prescaler Oscillation Start-up Timer OST Period 33* T Power-up Timer Period PWRT ...
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... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC12F629/675 Min Typ† ...
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... PIC12F629/675 TABLE 12-6: COMPARATOR SPECIFICATIONS Comparator Specifications Sym Characteristics V Input Offset Voltage OS V Input Common Mode Voltage CM C Common Mode Rejection Ratio MRR (1) T Response Time Comparator Mode Change Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (V ...
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... — REF — — 10 kΩ 10 — 1000 μA μA — — pin, whichever is selected as reference input. REF DD PIC12F629/675 Conditions = 5.0V REF = 5.0V REF V = 5.0V REF = 5.0V REF = 5.0V REF ≤ V ≤ AIN REF Absolute minimum to ensure 10-bit accuracy During V acquisition. AIN ...
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... PIC12F629/675 FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (T OSC Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. 130 T A/D Clock Period AD 130 ...
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... T AD (Note 2) 11.5 — μs μs 5* — — — — — OSC CY cycle. CY PIC12F629/675 NEW_DATA DONE Conditions ≥ 3.0V V REF V full range REF ADCS<1:0> (RC mode 2. 5.0V DD The minimum time is the amplifier settling time. This may be used if the “ ...
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... PIC12F629/675 NOTES: DS41190E-page 102 © 2007 Microchip Technology Inc. ...
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... FIGURE 13-1: TYPICAL I PD 6.0E-09 5.0E-09 4.0E-09 3.0E-09 2.0E-09 1.0E-09 0.0E+00 2 2.5 FIGURE 13-2: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5 © 2007 Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD PIC12F629/675 DD - 5.5 85 5.0 5.5 DS41190E-page 103 ...
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... PIC12F629/675 FIGURE 13-3: TYPICAL I PD 4.0E-06 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2.0 2.5 FIGURE 13-4: MAXIMUM I PD 1.0E-07 9.0E-08 8.0E-08 7.0E-08 6.0E-08 5.0E-08 4.0E-08 3.0E-08 2.0E-08 1.0E-08 0.0E+00 2 2.5 DS41190E-page 104 vs. V OVER TEMP (+125°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (-40°C TO +25°C) DD Maximum Baseline 3.5 4 4.5 V (V) DD 125 5.0 5.5 - 5.5 © 2007 Microchip Technology Inc. ...
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... FIGURE 13-5: MAXIMUM I PD 9.0E-07 8.0E-07 7.0E-07 6.0E-07 5.0E-07 4.0E-07 3.0E-07 2.0E-07 1.0E-07 0.0E+00 2.0 2.5 FIGURE 13-6: MAXIMUM I PD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5 © 2007 Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD PIC12F629/675 85 5.0 5.5 125 5.0 5.5 DS41190E-page 105 ...
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... PIC12F629/675 FIGURE 13-7: TYPICAL I PD 130 120 110 100 3.5 FIGURE 13-8: TYPICAL I PD 1.8E-05 1.6E-05 1.4E-05 1.2E-05 1.0E-05 8.0E-06 6.0E-06 4.0E-06 2.0E-06 0.0E+00 2.0 2.5 DS41190E-page 106 WITH BOD ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical BOD 4.5 V (V) DD WITH CMP ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical Comparator ...
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... FIGURE 13-9: TYPICAL I PD 5.0E-09 4.5E-09 4.0E-09 3.5E-09 3.0E-09 2.5E-09 2.0E-09 1.5E-09 1.0E-09 5.0E-10 0.0E+00 2 2.5 FIGURE 13-10: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5 © 2007 Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A 3.5 4 4.5 V (V) DD PIC12F629/675 - 5 5.5 DS41190E-page 107 ...
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... PIC12F629/675 FIGURE 13-11: TYPICAL I PD 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2 2.5 FIGURE 13-12: TYPICAL KHZ, C1 AND C2=50 pF) 1.20E-05 1.00E-05 8.00E-06 6.00E-06 4.00E-06 2.00E-06 0.00E+00 2.0 2.5 DS41190E-page 108 WITH A/D ENABLED vs. V OVER TEMP (+125°C) DD Typical A 3.5 4 4.5 V (V) DD WITH T1 OSC ENABLED vs Typical 3.0 3.5 4.0 4.5 V (V) DD 125 5 5.5 OVER TEMP (-40°C TO +125°C), ...
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... Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT 3.5 4 4.5 V (V) DD PIC12F629/675 - 125 5 5.5 - 125 5 5.5 DS41190E-page 109 ...
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... PIC12F629/675 MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1 μ F AND FIGURE 13-15: 0.01 μ F DECOUPLING (V 4.20E+06 4.15E+06 4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 -40°C FIGURE 13-16: MAXIMUM AND MINIMUM INTOSC FREQ vs. V DECOUPLING (+25°C) 4.20E+06 4.15E+06 4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 2 ...
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... FIGURE 13-17: TYPICAL WDT PERIOD vs 2.5 © 2007 Microchip Technology Inc. (-40 ° +125 ° WDT Time-out 3 3.5 4 4.5 V (V) DD PIC12F629/675 - 125 5 5.5 DS41190E-page 111 ...
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... PIC12F629/675 NOTES: DS41190E-page 112 © 2007 Microchip Technology Inc. ...
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... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. PIC12F629/675 Example 12F629-I /017 e 3 ...
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... PIC12F629/675 14.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE ...
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... N e 1.27 BSC A – A2 1.25 A1 0.10 E 6.00 BSC E1 3.90 BSC D 4.90 BSC h 0.25 L 0.40 L1 1.04 REF φ 0° c 0.17 b 0.31 α 5° β 5° PIC12F629/675 α c β NOM MAX 8 – 1.75 – – – 0.25 – 0.50 – 1.27 – 8° – 0.25 – 0.51 – 15° – 15° Microchip Technology Drawing C04-057B DS41190E-page 115 ...
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... PIC12F629/675 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N NOTE TOP VIEW A3 Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length ...
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... PIC; Revised Product ID example (b). Revision E (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section. © 2007 Microchip Technology Inc. PIC12F629/675 APPENDIX B: DEVICE DIFFERENCES The differences between the PIC12F629/675 devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Feature PIC12F629 A/D No DS41190E-page 117 ...
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... PIC12F629/675 APPENDIX C: DEVICE MIGRATIONS This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable DS41190E-page 118 APPENDIX D: MIGRATING FROM OTHER PIC DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX family of devices ...
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... Write Verify ................................................................. 49 Code Protection .................................................................. 67 Comparator ......................................................................... 35 Associated Registers .................................................. 40 Configuration............................................................... 37 Effects of a RESET ..................................................... 39 I/O Operating Modes................................................... 37 Interrupts..................................................................... 40 © 2007 Microchip Technology Inc. PIC12F629/675 Operation.................................................................... 36 Operation During SLEEP............................................ 39 Output......................................................................... 38 Reference ................................................................... 39 Response Time .......................................................... 39 Comparator Specifications................................................ 100 Comparator Voltage Reference Specifications................. 100 Configuration Bits ............................................................... 52 Configuring the Voltage Reference..................................... 39 Crystal Operation ...
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... CONFIG (Configuration Word) ................................... 52 EEADR (EEPROM Address) ...................................... 47 EECON1 (EEPROM Control) ..................................... 48 EEDAT (EEPROM Data) ............................................ 47 INTCON (Interrupt Control)......................................... 13 IOC (Interrupt-on-Change GPIO)................................ 21 Maps PIC12F629 ........................................................... 8 PIC12F675 ........................................................... 8 OPTION_REG (Option) ........................................ 12, 28 OSCCAL (Oscillator Calibration) ................................ 16 PCON (Power Control) ............................................... 16 PIE1 (Peripheral Interrupt Enable 1)........................... 14 PIR1 (Peripheral Interrupt 1)....................................... 15 STATUS ..................................................................... 11 T1CON (Timer1 Control) ...
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... Time-out Sequence on Power-up (MCLR Tied to V ).................................................... 60 DD Timer0 and Timer1 External Clock ............................. 99 Timer1 Incrementing Edge.......................................... 31 Timing Parameter Symbology............................................. 93 V Voltage Reference Accuracy/Error ..................................... 39 W Watchdog Timer Summary of Registers ................................................ 65 Watchdog Timer (WDT) ...................................................... 64 WWW, On-Line Support ....................................................... 3 © 2007 Microchip Technology Inc. PIC12F629/675 DS41190E-page 121 ...
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... PIC12F629/675 NOTES: DS41190E-page 122 © 2007 Microchip Technology Inc. ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC12F629/675 should contact their distributor, DS41190E-page 123 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC12F629/675 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. © 2007 Microchip Technology Inc. XXX Examples: Pattern a) PIC12F629 package, 20 MHz, QTP pattern #301 b) PIC12F675 package, 20 MHz range DD PIC12F629/675 -E/P 301 = Extended Temp., PDIP -I/SN = Industrial Temp., SOIC DS41190E-page 125 ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...