PIC12F629-I/SN Microchip Technology, PIC12F629-I/SN Datasheet
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PIC12F629-I/SN Summary of contents
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... Microchip Technology Inc. PIC12F629/675 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41190G ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC12F675 1024 * 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. 2010 Microchip Technology Inc. PIC12F629/675 Low-Power Features: • Standby Current 2.0V, typical • Operating Current: - 8.5 ...
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... PIC12F629/675 Pin Diagrams 8-pin PDIP, SOIC, DFN-S, DFN GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/V GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/V DS41190G-page GP0/CIN+/ICSPDAT 2 7 GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT GP0/AN0/CIN+/ICSPDAT 3 6 GP1/AN1/CIN-/V REF 4 5 GP2/AN2/T0CKI/INT/COUT PP /ICSPCLK 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC12F629/675 DS41190G-page 5 ...
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... PIC12F629/675 NOTES: DS41190G-page 6 2010 Microchip Technology Inc. ...
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... The PIC12F629 and PIC12F675 devices are covered by this Data Sheet. They are identical, except the PIC12F675 has a 10-bit A/D converter. They come in 8-pin PDIP, SOIC, MLF-S and DFN packages. Figure 1-1 shows a block diagram of the PIC12F629/ 675 devices. Table 1-1 shows the pinout description. 8 Data Bus ...
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... PIC12F629/675 TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION Name Function GP0/AN0/CIN+/ICSPDAT GP0 AN0 CIN+ ICSPDAT GP1/AN1/CIN-/V / GP1 REF ICSPCLK AN1 CIN- V REF ICSPCLK GP2/AN2/T0CKI/INT/COUT GP2 AN2 T0CKI INT COUT GP3/MCLR/V GP3 PP MCLR V PP GP4/AN3/T1G/OSC2/ GP4 CLKOUT AN3 T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 ...
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... MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F629/675 devices have a 13-bit program counter capable of addressing program memory space. Only the first (0000h-03FFh) for the PIC12F629/675 devices is physically imple- mented. Accessing a location above these boundaries will cause a wrap-around within the first space. ...
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... The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS41190G-page 10 FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F629/675 File Address (1) Indirect addr. 00h Indirect addr. TMR0 ...
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... CMIF — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC CINV CIS CM2 — — — CHS1 CHS0 0 ’ unchanged unknown value depends on condition, 0 ’. PIC12F629/675 Value on Bit 1 Bit 0 POR, BOD 20,61 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx GPIO1 GPIO0 --xx xxxx — ...
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... PIC12F629/675 TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (1) 80h INDF Addressing this Location uses Contents of FSR to Address Data Memory 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h STATUS (2) IRP RP1 ...
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... Status bits. For other instructions not affect- ing any Status bits, see the “Instruction Set Summary”. Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC12F629/675 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products ...
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... PIC12F629/675 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External GP2/INT interrupt • TMR0 • Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG: OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 R/W-1 ...
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... T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized before clearing T0IF bit. 2010 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... PIC12F629/675 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 U-0 EEIE ADIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
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... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow 2010 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... PIC12F629/675 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON Register bits are shown in Register 2-6. REGISTER 2-6: ...
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... Microchip Technology Inc. PIC12F629/675 2.3.2 STACK The PIC12F629/675 family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed interrupt causes a branch ...
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... Writing to the INDF register indirectly results operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-2. FIGURE 2-2: DIRECT/INDIRECT ADDRESSING PIC12F629/675 Direct Addressing (1) From Opcode RP1 RP0 ...
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... MOVLW 0Ch MOVWF TRISIO 3.2 Additional Pin Functions Every GPIO pin on the PIC12F629/675 has an interrupt-on-change option and every GPIO pin, except GP3, has a weak pull-up option. The next two sections describe these functions. 3.2.1 WEAK PULL-UP Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up ...
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... PIC12F629/675 REGISTER 3-2: TRISIO: GPIO TRI-STATE REGISTER (ADDRESS: 85h) U-0 U-0 R/W-1 TRISIO5 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISIO<5:0>: General Purpose I/O Tri-State Control bit ...
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... Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2010 Microchip Technology Inc. PIC12F629/675 This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of GPIO ...
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... PIC12F629/675 3.3 Pin Descriptions and Diagrams Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. ...
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... Figure 3-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: Data Bus RD TRISIO PORT Weak IOC RD IOC V DD Interrupt-on-Change I/O pin PIC12F629/675 PP BLOCK DIAGRAM OF GP3 MCLRE Reset I/O pin V SS MCLRE PORT DS41190G-page 25 ...
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... PIC12F629/675 3.3.5 GP4/AN3/T1G/OSC2/CLKOUT Figure 3-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D (PIC12F675 only) • a TMR1 gate input • a crystal/resonator connection • a clock output ...
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... WPU — — 96h IOC — — 9Fh ANSEL — ADCS2 Legend unknown unchanged unimplemented locations read as ‘ 2010 Microchip Technology Inc. PIC12F629/675 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GP5 GP4 GP3 GP2 GP1 T0IE INTE GPIE T0IF INTF — ...
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... PIC12F629/675 NOTES: DS41190G-page 28 2010 Microchip Technology Inc. ...
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... The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut- off during Sleep 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA PIC12F629/675 edge (T0SE) control bit ® Reference Manual, Data Bus 8 SYNC 2 TMR0 Cycles Set Flag bit T0IF ...
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... PIC12F629/675 4.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... OPTION_REG GPPU INTEDG 85h TRISIO — — Legend: — = Unimplemented locations, read as ‘ Shaded cells are not used by the Timer0 module. 2010 Microchip Technology Inc. PIC12F629/675 EXAMPLE 4-1: BCF STATUS,RP0 CLRWDT CLRF TMR0 BSF STATUS,RP0 MOVLW b’00101111’ ;Required if desired ...
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... PIC12F629/675 5.0 TIMER1 MODULE WITH GATE CONTROL The PIC12F629/675 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • ...
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... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010 Microchip Technology Inc. PIC12F629/675 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...
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... PIC12F629/675 REGISTER 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 R/W-0 R/W-0 — TMR1GE T1CKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored ...
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... INTE GPIE T0IF — — CMIF — — — CMIE — 0 ’. Shaded cells are not used by the Timer1 module. PIC12F629/675 Value on Value on Bit 1 Bit 0 all other POR, BOD Resets INTF GPIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — ...
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... PIC12F629/675 NOTES: DS41190G-page 36 2010 Microchip Technology Inc. ...
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... COMPARATOR MODULE The PIC12F629/675 devices have one analog comparator. The inputs to the comparator are multiplexed with the GP0 and GP1 pins. There is an on-chip Comparator Voltage Reference that can also be applied to an input of the comparator. In addition, GP2 can be configured as the comparator output. ...
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... PIC12F629/675 6.1 Comparator Operation A single comparator is shown in Figure 6-1, along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
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... D Multiplexed Input with Internal Reference and Output CM2:CM0 = 101 GP1/CIN- A COUT GP0/CIN+ A GP2/COUT D Multiplexed Input with Internal Reference CM2:CM0 = 110 GP1/CIN- A COUT GP0/CIN+ A GP2/COUT D PIC12F629/675 0 Off (Read as ‘ ’) COUT From CV Module REF 0 CIS = 1 CIS = COUT From CV Module REF 0 CIS = 1 CIS = ...
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... PIC12F629/675 6.3 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 6-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V . The analog input, therefore, must be between SS V and the input voltage deviates from this ...
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... To minimize power consumption while in Sleep mode, turn off the comparator, CM2:CM0 = 111, and voltage refer- ence, VRCON<7> 2010 Microchip Technology Inc. PIC12F629/675 The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range ...
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... PIC12F629/675 REGISTER 6-2: VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) R/W-0 U-0 R/W-0 VREN — VRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 VREN: CV Enable bit REF circuit powered on REF circuit powered down REF bit 6 Unimplemented: Read as ‘ ...
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... F (dedicated internal RC oscillator) RC For correct conversion, the A/D conversion clock (1/T ) must be selected to ensure a minimum T AD 1.6 s. Table 7-1 shows a few T selected frequencies. bits PIC12F629/675 pin. Figure 7-1 REF 10 10 pin is the reference; REF is the reference. . The source AD of ...
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... PIC12F629/675 TABLE 7-1: T vs. DEVICE OPERATING FREQUENCIES AD A/D Clock Source ( Operation ADCS2:ADCS0 2 T 000 OSC 4 T 100 OSC 8 T 001 OSC 16 T 101 OSC 32 T 010 OSC 64 T 110 OSC A/D RC x11 Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical T 2: These values violate the minimum required T 3: For faster conversion times, the selection of another clock source is recommended ...
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... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current 2010 Microchip Technology Inc. PIC12F629/675 U-0 R/W-0 R/W-0 — CHS1 CHS0 U = Unimplemented bit, read as ‘ ...
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... PIC12F629/675 REGISTER 7-2: ANSEL: ANALOG SELECT REGISTER (ADDRESS: 9Fh) U-0 R/W-0 R/W-0 — ADCS2 ADCS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = Fosc/2 ...
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... Mid-Range Reference Manual (DS33023). ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD V DD Sampling Switch LEAKAGE V = 0.6V T ± 500 PIC12F629/675 the minimum acquisition time, , see ACQ SS C HOLD = DAC capacitance = 120 Sampling Switch (k) DS41190G-page 47 ...
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... PIC12F629/675 7.3 A/D Operation During Sleep The A/D converter module can operate during Sleep. This requires the A/D clock source to be set to the internal RC oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion ...
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... EEDATA • EEADR EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC12F629/675 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. REGISTER 8-1: EEDAT: EEPROM DATA REGISTER (ADDRESS: 9Ah) ...
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... PIC12F629/675 8.1 EEADR The EEADR register can address maximum of 128 bytes of data EEPROM. Only seven of the eight bits in the register (EEADR<6:0>) are required. The MSb (bit 7) is ignored. The upper bit should always be ‘0’ to remain upward compatible with devices that have more data EEPROM memory ...
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... On power-up, WREN is cleared. Also, the Power-up Timer EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: • brown-out • power glitch • software malfunction PIC12F629/675 WRITE VERIFY STATUS,RP0 ;Bank 0 ;Any code STATUS,RP0 ;Bank 1 READ EEDATA,W ;EEDATA not changed ...
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... PIC12F629/675 8.7 Data EEPROM Operation During Code Protect Data memory can be code protected by programming the CPD bit to ‘0’. When the data memory is code protected, the CPU is able to read and write data to the data EEPROM recommended to code protect the program memory when code protecting data memory ...
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... ID Locations • In-Circuit Serial Programming 2010 Microchip Technology Inc. PIC12F629/675 The PIC12F629/675 has a Watchdog Timer that is controlled by Configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable ...
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... Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as spec- ified in the PIC12F629/675 Programming Specification. These bits are reflected in an export of the Configuration Word. Microchip Development Tools maintain all Calibration bits to factory settings. ...
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... Oscillator Configurations 9.2.1 OSCILLATOR TYPES The PIC12F629/675 can be operated in eight different oscillator option modes. The user can program three Configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • LP Low-Power Crystal • XT Crystal/Resonator • HS High-Speed Crystal/Resonator • RC External Resistor/Capacitor (2 modes) • ...
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... EXAMPLE 9-1: BSF CALL MOVWF BCF Internal Clock 9.2.6 CLKOUT The PIC12F629/675 devices can be configured to provide a clock out signal in the INTOSC and RC oscillator modes. When configured, the oscillator frequency divided by four (F GP4/OSC2/CLKOUT pin. F purposes or to synchronize other logic. OSCILLATOR Z /4. OSC ...
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... Reset The PIC12F629/675 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Detect (BOD) Some registers are not affected in any Reset condition; ...
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... PIC12F629/675 9.3.1 MCLR PIC12F629/675 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. ...
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... Then bringing MCLR high will begin execution immediately (see Figure 9-8). This is useful for testing purposes or to synchronize more than one PIC12F629/675 device operating in parallel. Table 9-6 shows the Reset conditions for some special registers, while Table 9-7 shows the Reset conditions for all the registers ...
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... PIC12F629/675 TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration PWRTE = 0 XT, HS PWRT 1024•T RC, EC, INTOSC T PWRT TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOD Legend unchanged unknown TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT Address Name Bit 7 Bit 6 03h STATUS ...
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... PIC12F629/675 • Wake-up from Sleep through interrupt • Wake-up from Sleep through WDT Time-out uuuu uuuu — uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu ...
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... PIC12F629/675 FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V ...
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... Interrupts The PIC12F629/675 has 7 sources of interrupt: • External Interrupt GP2/INT • TMR0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt (PIC12F675 only) • TMR1 Overflow Interrupt • EEPROM Data Write Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits ...
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... PIC12F629/675 FIGURE 9-10: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE ADIF (1) ADIE EEIF EEIE Note 1: PIC12F675 only. DS41190G-page 64 T0IF Wake-up (If in Sleep mode) T0IE INTF INTE GPIF GPIE PEIE GIE ...
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... Module (PIC12F675 only)” for operation of the A/D converter interrupt. T0IE Interrupt Latency Inst (PC+1) — Inst (PC) Dummy Cycle Dummy Cycle . Synchronous latency = where PIC12F629/675 “Comparator Interrupts” for 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) = instruction cycle time. Latency CY DS41190G-page 65 ...
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... PIC12F629/675 TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS Address Name Bit 7 Bit 6 0Bh, 8Bh INTCON GIE PEIE 0Ch PIR1 EEIF ADIF 8Ch PIE1 EEIE ADIE Legend unknown unchanged unimplemented read as ‘ Shaded cells are not used by the interrupt module. 9.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack ...
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... Name Bit 7 Bit 6 81h OPTION_REG GPPU INTEDG 2007h Config. bits CP BODEN MCLRE PWRTE WDTE Legend Unchanged, shaded cells are not used by the Watchdog Timer. 2010 Microchip Technology Inc. PIC12F629/675 1 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA Bit 5 Bit 4 Bit 3 ...
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... PIC12F629/675 9.7 Power-Down Mode (Sleep) The Power-down mode is entered by executing a instruction. SLEEP If the Watchdog Timer is enabled: • WDT will be cleared but keeps running • PD bit in the STATUS register is cleared • TO bit is set • Oscillator driver is turned off • I/O ports maintain the status they had before ...
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... Program/Verify. Only the Least Significant 7 bits of the ID locations are used. 9.10 In-Circuit Serial Programming The PIC12F629/675 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for: • ...
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... PIC12F629/675 NOTES: DS41190G-page 70 2010 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC12F629/675 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC12F629/675 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction ...
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... PIC12F629/675 TABLE 10-2: PIC12F629/675 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Z Description: AND the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’. 2010 Microchip Technology Inc. PIC12F629/675 BCF Bit Clear f Syntax: [label] BCF f,b 0 f 127 Operands: 0 ...
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... PIC12F629/675 BTFSC Bit Test, Skip if Clear Syntax: [label] BTFSC f,b 0 f 127 Operands: 0 b 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the ...
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... Description: The contents of register ‘f’ are incremented. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed back in register ‘f’. 2010 Microchip Technology Inc. PIC12F629/675 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 f 127 Operands: d ...
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... PIC12F629/675 MOVF Move f Syntax: [ label ] MOVF f,d 0 f 127 Operands: d [0,1] (f) (dest) Operation: Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status the destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected ...
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... This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 2010 Microchip Technology Inc. PIC12F629/675 RETLW Return with literal in W Syntax: [ label ] RETLW k 0 k 255 Operands: k (W); Operation: TOS PC Status Affected: None Description: The W register is loaded with the eight-bit literal ‘ ...
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... PIC12F629/675 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d 0 f 127 Operands: d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘d’ the result is placed in the W register. If ‘ ...
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... Operation: Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. 2010 Microchip Technology Inc. PIC12F629/675 XORWF Exclusive OR W with f Syntax: [label] XORWF 0 f 127 Operands: d [0,1] (W) .XOR. (f) ...
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... PIC12F629/675 NOTES: DS41190G-page 80 2010 Microchip Technology Inc. ...
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... Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. PIC12F629/675 ® DS41190G-page 81 ...
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... PIC12F629/675 11.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
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... In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. variable PIC12F629/675 ® Flash microcon- ® DSCs with the powerful, yet easy- PICkit ...
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... PIC12F629/675 11.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
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... DD - DIS the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. should be used when applying a “low” level to the MCLR pin, rather than . SS PIC12F629/675 + 0.3V {( ( ...
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... PIC12F629/675 FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C T ...
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... FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2010 Microchip Technology Inc. PIC12F629/675 Frequency (MHz) 20 DS41190G-page 87 ...
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... PIC12F629/675 12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001A D001B D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD ...
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... DC Characteristics: PIC12F629/675-I (Industrial) Param Device Characteristics No. D010 Supply Current ( D011 D012 D013 D014 D015 D016 D017 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all I from rail-to-rail ...
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... PIC12F629/675 12.3 DC Characteristics: PIC12F629/675-I (Industrial) Param Device Characteristics No. D020 Power-down Base Current ( D021 D022 D023 D024 D025 D026 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base I peripheral is enabled. The peripheral ...
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... DC Characteristics: PIC12F629/675-E (Extended) Param Device Characteristics No. D010E Supply Current ( D011E D012E D013E D014E D015E D016E D017E † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all I from rail-to-rail ...
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... PIC12F629/675 12.5 DC Characteristics: PIC12F629/675-E (Extended) Param Device Characteristics No. D020E Power-down Base Current ( D021E D022E D023E D024E D025E D026E † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base I peripheral is enabled. The peripheral ...
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... DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) D033A OSC1 (HS mode) Input High Voltage V I/O ports ...
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... PIC12F629/675 12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.) DC CHARACTERISTICS Param Sym Characteristic No. Capacitive Loading Specs on Output Pins D100 C OSC2 pin OSC2 D101 C All I/O pins IO Data EEPROM Memory D120 E Byte Endurance D D120A E Byte Endurance D D121 V V for Read/Write DRW DD D122 T Erase/Write cycle time ...
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... Fall H High I Invalid (High-Impedance) L Low FIGURE 12-4: LOAD CONDITIONS Load Condition 1 Pin R = 464 for all pins for OSC2 output 2010 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-Impedance Load Condition Pin V SS PIC12F629/675 DS41190G-page 95 ...
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... PIC12F629/675 12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED) FIGURE 12-5: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No. F External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period OSC (1) Oscillator Period Instruction Cycle Time 3 TosL, External CLKIN (OSC1) High ...
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... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2010 Microchip Technology Inc. PIC12F629/675 Freq. Min Typ† Max Units Tolerance ...
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... PIC12F629/675 FIGURE 12-6: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O pin (Input) I/O pin Old Value (Output) TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic No. 10 TosH2ckL OSC1 to CLOUT 11 TosH2ckH OSC1 to CLOUT 12 TckR CLKOUT rise time ...
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... Watchdog Timer Reset I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) Reset (due to BOD) Note delay only if PWRTE bit in Configuration Word is programmed to ‘ 2010 Microchip Technology Inc. PIC12F629/675 (Device not in Brown-out Detect time-out 0 ’. 34 DS41190G-page 99 ...
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... PIC12F629/675 TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT DETECT REQUIREMENTS Param Sym Characteristic No MCLR Pulse Width (low Watchdog Timer Time-out WDT Period (No Prescaler Oscillation Start-up Timer OST Period 33* T Power-up Timer Period PWRT 34 T I/O High-impedance from ...
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... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2010 Microchip Technology Inc. PIC12F629/675 Min Typ† ...
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... PIC12F629/675 TABLE 12-6: COMPARATOR SPECIFICATIONS Comparator Specifications Sym Characteristics V Input Offset Voltage OS V Input Common Mode Voltage CM C Common Mode Rejection Ratio MRR (1) T Response Time Comparator Mode Change Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (V ...
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... DD V — REF — — 10 k A 10 — 1000 A — — pin, whichever is selected as reference input. REF DD PIC12F629/675 Conditions = 5.0V REF = 5.0V REF V = 5.0V REF = 5.0V REF = 5.0V REF V AIN REF Absolute minimum to ensure 10-bit accuracy During V acquisition ...
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... PIC12F629/675 FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (T OSC Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS ...
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... T AD s (Note 2) 11.5 — s 5* — — — — — OSC CY cycle. CY PIC12F629/675 NEW_DATA DONE Conditions 3.0V V REF V full range REF ADCS<1:0> (RC mode 2. 5.0V DD The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i ...
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... PIC12F629/675 NOTES: DS41190G-page 106 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD PIC12F629/675 DD - 5.5 85 5.0 5.5 DS41190G-page 107 ...
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... PIC12F629/675 FIGURE 13-3: TYPICAL I vs 4.0E-06 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2.0 2.5 FIGURE 13-4: MAXIMUM I PD 1.0E-07 9.0E-08 8.0E-08 7.0E-08 6.0E-08 5.0E-08 4.0E-08 3.0E-08 2.0E-08 1.0E-08 0.0E+00 2 2.5 DS41190G-page 108 OVER TEMP (+125°C) DD Typical Baseline ...
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... Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD PIC12F629/675 85 5.0 5.5 125 5.0 5.5 DS41190G-page 109 ...
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... PIC12F629/675 FIGURE 13-7: TYPICAL I WITH BOD ENABLED vs 130 120 110 100 3.5 FIGURE 13-8: TYPICAL I WITH CMP ENABLED vs 1.8E-05 1.6E-05 1.4E-05 1.2E-05 1.0E-05 8.0E-06 6.0E-06 4.0E-06 2.0E-06 0.0E+00 2.0 2.5 DS41190G-page 110 OVER TEMP (-40°C TO +125°C) DD Typical BOD 4 (V) DD OVER TEMP (-40°C TO +125°C) ...
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... Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A 3.5 4 4.5 V (V) DD PIC12F629/675 - 5 5.5 DS41190G-page 111 ...
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... PIC12F629/675 FIGURE 13-11: TYPICAL I WITH A/D ENABLED vs 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2 2.5 FIGURE 13-12: TYPICAL I WITH T1 OSC ENABLED vs kHZ, C1 AND C2=50 pF) 1.20E-05 1.00E-05 8.00E-06 6.00E-06 4.00E-06 2.00E-06 0.00E+00 2.0 2.5 DS41190G-page 112 OVER TEMP (+125°C) DD Typical A/D I ...
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... Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT 3.5 4 4.5 V (V) DD PIC12F629/675 - 125 5 5.5 - 125 5 5.5 DS41190G-page 113 ...
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... PIC12F629/675 MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1 F AND FIGURE 13-15: 0.01 F DECOUPLING (V 4.20E+06 4.15E+06 4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 -40°C MAXIMUM AND MINIMUM INTOSC FREQ vs. V FIGURE 13-16: DECOUPLING (+25°C) 4.20E+06 4.15E+06 4.10E+06 4 ...
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... FIGURE 13-17: TYPICAL WDT PERIOD vs 2.5 2010 Microchip Technology Inc. (-40 +125 WDT Time-out 3 3.5 4 4.5 V (V) DD PIC12F629/675 - 125 5 5.5 DS41190G-page 115 ...
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... PIC12F629/675 NOTES: DS41190G-page 116 2010 Microchip Technology Inc. ...
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... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. PIC12F629/675 Example 12F629-I /017 e 3 ...
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... PIC12F629/675 14.2 Package Details The following sections give the technical details of the packages. N NOTE DS41190G-page 118 2010 Microchip Technology Inc. ...
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... N NOTE 2010 Microchip Technology Inc φ PIC12F629/675 α c β DS41190G-page 119 ...
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... PIC12F629/675 DS41190G-page 120 2010 Microchip Technology Inc. ...
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... D N NOTE TOP VIEW A3 2010 Microchip Technology Inc. PIC12F629/675 EXPOSED PAD BOTTOM VIEW A A1 NOTE NOTE DS41190G-page 121 ...
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... PIC12F629/675 DS41190G-page 122 2010 Microchip Technology Inc. ...
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... Plastic Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc. PIC12F629/675 Microchip Technology Drawing C04-131E Sheet DS41190G-page 123 ...
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... PIC12F629/675 8-Lead Plastic Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41190G-page 124 Microchip Technology Drawing C04-131E Sheet 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC12F629/675 DS41190G-page 125 ...
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... PIC12F629/675 NOTES: DS41190G-page 126 2010 Microchip Technology Inc. ...
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... Revision G (03/2010) Updated the Instruction Set Summary section, adding pages 76 and 77. 2010 Microchip Technology Inc. PIC12F629/675 APPENDIX B: DEVICE DIFFERENCES The differences between the PIC12F629/675 devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Feature PIC12F629 A/D No ...
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... PIC12F629/675 APPENDIX C: DEVICE MIGRATIONS This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable DS41190G-page 128 APPENDIX D: MIGRATING FROM OTHER PIC DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX family of devices ...
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... Saving STATUS and W Registers in RAM ................. 66 Write Verify ................................................................. 51 Code Protection .................................................................. 69 Comparator ......................................................................... 37 Associated Registers .................................................. 42 Configuration............................................................... 39 Effects of a RESET ..................................................... 41 I/O Operating Modes................................................... 39 2010 Microchip Technology Inc. PIC12F629/675 Interrupts .................................................................... 42 Operation.................................................................... 38 Operation During SLEEP............................................ 41 Output......................................................................... 40 Reference ................................................................... 41 Response Time .......................................................... 41 Comparator Specifications................................................ 102 Comparator Voltage Reference Specifications................. 102 Configuration Bits ...
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... ANSEL (Analog Select) .............................................. 46 CONFIG (Configuration Word) ................................... 54 EEADR (EEPROM Address) ...................................... 50 EECON1 (EEPROM Control) ..................................... 51 EEDAT (EEPROM Data) ............................................ 49 INTCON (Interrupt Control)......................................... 15 IOCB (Interrupt-on-Change GPIO) ............................. 24 Maps PIC12F629 ......................................................... 10 PIC12F675 ......................................................... 10 OPTION_REG (Option) .................................. 14, 30, 31 OSCCAL (Oscillator Calibration) ................................ 18 PCON (Power Control) ............................................... 18 PIE1 (Peripheral Interrupt Enable 1)........................... 16 PIR1 (Peripheral Interrupt 1)....................................... 17 STATUS ..................................................................... 14 T1CON (Timer1 Control) ...
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... Timing Parameter Symbology............................................. 95 TRISIO — GPIO Tri-state REGISTER (Address 85H) ............................................................................ 22 V Voltage Reference Accuracy/Error ..................................... 41 W Watchdog Timer Summary of Registers ................................................ 67 Watchdog Timer (WDT) ...................................................... 66 WPU — Weak pull-up Register (ADDRESS 95h)............................................................................. 22 WWW Address.................................................................. 133 WWW, On-Line Support ....................................................... 5 2010 Microchip Technology Inc. PIC12F629/675 DS41190G-page 131 ...
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... PIC12F629/675 NOTES: DS41190G-page 132 2010 Microchip Technology Inc. ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC12F629/675 should contact their distributor, DS41190G-page 133 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC12F629/675 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. 2010 Microchip Technology Inc. XXX Examples: Pattern a) b) range DD (Industrial) (Extended) PIC12F629/675 . PIC12F629 - E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301. PIC12F675 - I/SN = Industrial temp., SOIC package, 20 MHz. DS41190G-page 135 ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...