SAK-XC2766X-96F66L AC Infineon Technologies, SAK-XC2766X-96F66L AC Datasheet - Page 97

• Manufacturer Part Number: SAK-XC2766X-96F66L AC
• Description: IC MCU 16BIT FLASH PG-LQFP-100
• Manufacturer: Infineon Technologies
• Series: XC27x6Xr

Specifications of SAK-XC2766X-96F66L AC

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 51K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KX2766X96F66LACXT; SAK-XC2766X-96F66LACINTR; SP000366063

Variable Memory Cycles
External bus cycles of the XC2766X are executed in five consecutive cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module
using the READY handshake input.
This table provides a summary of the phases and the ranges for their length.
Table 28
Bus Cycle Phase
Address setup phase, the standard duration of this
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
Command delay phase
Write Data setup/MUX Tristate phase
Access phase
Address/Write Data hold phase
Note: The bandwidth of a parameter (from minimum to maximum value) covers the
Timing values are listed in
verified by characterization. They are not subject to production test.
Data Sheet
whole operating range (temperature, voltage) as well as process variations. Within
a given device, however, this bandwidth is smaller than the specified range. This
is also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Programmable Bus Cycle Phases (see timing diagrams)
Table 29
and
Table
95
30. The shaded parameters have been
Parameter Valid Values Unit
tpAB
tpC
tpD
tpE
tpF
XC2000 Family Derivatives
Electrical Parameters
0 … 3
0 … 1
0 … 3
1 … 2 (5)
1 … 32
V2.1, 2008-08
XC2766X
TCS
TCS
TCS
TCS
TCS