SAK-XC2766X-96F66L AC Infineon Technologies, SAK-XC2766X-96F66L AC Datasheet - Page 57

• Manufacturer Part Number: SAK-XC2766X-96F66L AC
• Description: IC MCU 16BIT FLASH PG-LQFP-100
• Manufacturer: Infineon Technologies
• Series: XC27x6Xr

Specifications of SAK-XC2766X-96F66L AC

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 51K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KX2766X96F66LACXT; SAK-XC2766X-96F66LACINTR; SP000366063

3.11
The XC2766X includes two USIC modules (USIC0, USIC1), each providing two serial
communication channels.
The Universal Serial Interface Channel (USIC) module is based on a generic data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent of the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and
outputs of each USIC channel can be assigned to different interface pins, providing great
flexibility to the application software. All assignments can be made during runtime.
Figure 10
The regular structure of the USIC module brings the following advantages:
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•
•
Data Sheet
Higher flexibility through configuration with same look-and-feel for data management
Reduced complexity for low-level drivers serving different protocols
Wide range of protocols with improved performances (baud rate, buffer handling)
Bus
Universal Serial Interface Channel Modules (USIC)
f
sys
General Structure of a USIC Module
Buffer & Shift Structure Protocol Preprocessors
DBU
DBU
0
1
Fractional
Control 0
Control 1
Dividers
DSU
DSU
0
1
55
Generators
Baud rate
PPP_C
PPP_D
PPP_C
PPP_D
PPP_A
PPP_B
PPP_A
PPP_B
XC2000 Family Derivatives
Functional Description
USIC_basic.vsd
Pins
V2.1, 2008-08
XC2766X