SAF-C161S-LM 3V AA Infineon Technologies, SAF-C161S-LM 3V AA Datasheet - Page 58
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
SAF-C161S-LM 3V AA
Manufacturer Part Number
SAF-C161S-LM 3V AA
Description
IC MCU 16BIT ROM/LESS MQFP-80-7
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161S-L25M_AA.pdf
(75 pages)
Specifications of SAF-C161S-LM 3V AA
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
ASC, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
63
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Packages
PG-MQFP-80
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
2.0 KByte
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
F161SLM3VAAXT
SAF-C161S-LM3VAA
SAF-C161S-LM3VAAINTR
SAF-C161S-LM3VAATR
SAF-C161S-LM3VAATR
SAFC161SLM3VAAXT
SP000014948
SAF-C161S-LM3VAA
SAF-C161S-LM3VAAINTR
SAF-C161S-LM3VAATR
SAF-C161S-LM3VAATR
SAFC161SLM3VAAXT
SP000014948
Table 17
ALE cycle time = 6 TCL + 2
Parameter
Data valid to WR
Data hold after WR
ALE rising edge after RD,
WR
Address hold after RD,
WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE fall. edge to RdCS,
WrCS (with RW delay)
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after
RdCS, WrCS (with RW
delay)
Address float after
RdCS, WrCS (no RW
delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data Sheet
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
1)
1)
1)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
22
23
25
27
38
39
40
42
43
44
45
46
47
48
49
t
A
+
t
C
CC 24 +
CC 36 +
CC 36 +
CC 36 +
CC -8 -
SR –
CC 57 +
CC 19 +
CC -6 +
CC –
CC –
SR –
SR –
CC 38 +
CC 63 +
+
t
F
Min.
Max. CPU Clock
(150 ns at 20 MHz CPU clock without waitstates)
= 20 MHz
t
54
t
A
t
t
t
t
t
t
t
t
A
C
F
F
F
F
A
C
C
Max.
–
–
–
–
10 -
47 +
+ 2
–
–
–
0
25
20 +
45 +
–
–
t
A
t
t
t
t
A
C
C
C
1 / 2TCL = 1 to 20 MHz
Min.
2TCL - 26
+
2TCL - 14
+
2TCL - 14
+
2TCL - 14
+
-8 -
–
3TCL - 18
+
TCL - 6
+
-6
+
–
–
–
–
2TCL - 12
+
3TCL - 12
+
Variable CPU Clock
t
t
t
t
t
t
t
t
t
C
F
F
F
F
A
A
C
C
t
A
Timing Characteristics
Max.
–
–
–
–
10 -
3TCL - 28
+
–
–
–
0
TCL
2TCL - 30
+
3TCL - 30
+
–
–
t
t
t
C
C
C
+ 2
t
V1.0, 2003-11
A
t
A
C161S
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns