SAF-C161S-LM 3V AA Infineon Technologies, SAF-C161S-LM 3V AA Datasheet - Page 48
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SAF-C161S-LM 3V AA
Manufacturer Part Number
SAF-C161S-LM 3V AA
Description
IC MCU 16BIT ROM/LESS MQFP-80-7
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161S-L25M_AA.pdf
(75 pages)
Specifications of SAF-C161S-LM 3V AA
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
ASC, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
63
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Packages
PG-MQFP-80
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
2.0 KByte
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
F161SLM3VAAXT
SAF-C161S-LM3VAA
SAF-C161S-LM3VAAINTR
SAF-C161S-LM3VAATR
SAF-C161S-LM3VAATR
SAFC161SLM3VAAXT
SP000014948
SAF-C161S-LM3VAA
SAF-C161S-LM3VAAINTR
SAF-C161S-LM3VAATR
SAF-C161S-LM3VAATR
SAFC161SLM3VAAXT
SP000014948
5
5.1
The internal operation of the C161S is controlled by the internal CPU clock
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 10
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C161S.
Note: The example for PLL operation shown in
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
Data Sheet
Phase Locked Loop Operation
f
f
Direct Clock Drive
f
f
Prescaler Operation
f
f
OSC
CPU
OSC
CPU
OSC
CPU
Timing Characteristics
Definition of Internal Timing
Generation Mechanisms for the CPU Clock
f
CPU
can be generated from the oscillator clock signal
44
Figure 10
refers to a PLL factor of 4.
TCL
f
Timing Characteristics
CPU
TCL
. This influence must
TCL
TCL
TCL
TCL
MCT04338
Figure
V1.0, 2003-11
f
CPU
f
C161S
OSC
. Both
10).
via