MC9S12H128VFVE Freescale Semiconductor, MC9S12H128VFVE Datasheet - Page 110

• Manufacturer Part Number: MC9S12H128VFVE
• Description: IC MCU 128K FLASH 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12H128VFVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 99
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 99
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 144LQFP
• Family Name: HCS12
• Maximum Speed: 16 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC9S12H256 Device User Guide — V01.20
The loop bandwidth f
typical values are 50. = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above inputs the resistance can be calculated as:
The capacitance C
The capacitance C
The stabilization delays shown in Table A-15 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.4.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock f
deviation from the reference clock f
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
110
s
p
can now be calculated as:
should be chosen in the range of:
C
f
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
<
------------------------------------------
C
2
s
+
n
ref
=
=
is measured and input voltage to the VCO is adjusted
C
1
--------------------- -
f
ref
s
f
------------ -
2
+
R
VCO
f
f
ref
C
20 C
=
2
2
R
2
---------------------------- -
=
----- -
50
1
2
p
0.516
-------------- -
f
K
C
n f
C
f
synr
C
R
s
<
C
;
10
------------- -
4 50
+
f
=
ref
1
0.9
;
=
0.9
cmp
, the