MC9S12E256MPVE Freescale Semiconductor, MC9S12E256MPVE Datasheet - Page 239

• Manufacturer Part Number: MC9S12E256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3.2.2
This register is reserved.
Read: always read $00
Write: unimplemented
7.3.2.3
Read: read zeroes when DJM is set
Write: unimplemented when DJM is set
The DAC data register is an 8-bit readable/writable register that stores the data to be converted when DJM
bit is clear. When the DACE bit is set, the value in this register is converted into an analog voltage such
that values from $00 to $FF result in equal voltage increments from V
this register reads zeroes and cannot be written.
Freescale Semiconductor
Module Base + 0x0002
Module Base + 0x0000
Reset
Reset
W
R
W
R
BIT 7
Reserved Register (DACC1)
DAC Data Register — Left Justified (DACD)
0
0
0
7
7
= Unimplemented or Reserved
BIT 6
Figure 7-5. DAC Data Register — Left Justified (DACD)
0
0
0
6
6
Figure 7-4. Reserved Register (DACC1)
BIT 5
MC9S12E256 Data Sheet, Rev. 1.08
0
0
0
5
5
BIT 4
0
0
0
4
4
BIT 3
3
0
0
3
0
Chapter 7 Digital-to-Analog Converter (DAC8B1CV1)
SSA
BIT 2
to V
0
0
0
2
2
REF
. When DJM bit is set,
BIT 1
0
0
0
1
1
BIT 0
0
0
0
0
0
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